qemu-rv32-spike.dts 1.1 KB

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  1. /dts-v1/;
  2. / {
  3. #address-cells = < 0x02 >;
  4. #size-cells = < 0x02 >;
  5. compatible = "ucbbar,spike-bare-dev";
  6. model = "ucbbar,spike-bare,qemu";
  7. chosen {
  8. bootargs = [ 00 ];
  9. };
  10. memory@80000000 {
  11. device_type = "memory";
  12. reg = < 0x00 0x80000000 0x00 0x8000000 >;
  13. };
  14. cpus {
  15. #address-cells = < 0x01 >;
  16. #size-cells = < 0x00 >;
  17. timebase-frequency = < 0x989680 >;
  18. cpu@0 {
  19. phandle = < 0x01 >;
  20. device_type = "cpu";
  21. reg = < 0x00 >;
  22. status = "okay";
  23. compatible = "riscv";
  24. riscv,isa = "rv32imafdcsu";
  25. mmu-type = "riscv,sv32";
  26. interrupt-controller {
  27. #interrupt-cells = < 0x01 >;
  28. interrupt-controller;
  29. compatible = "riscv,cpu-intc";
  30. phandle = < 0x02 >;
  31. };
  32. };
  33. cpu-map {
  34. cluster0 {
  35. core0 {
  36. cpu = < 0x01 >;
  37. };
  38. };
  39. };
  40. };
  41. soc {
  42. #address-cells = < 0x02 >;
  43. #size-cells = < 0x02 >;
  44. compatible = "simple-bus";
  45. ranges;
  46. clint@2000000 {
  47. interrupts-extended = < 0x02 0x03 0x02 0x07 >;
  48. reg = < 0x00 0x2000000 0x00 0x10000 >;
  49. compatible = "sifive,clint0\0riscv,clint0";
  50. };
  51. };
  52. htif {
  53. compatible = "ucb,htif0";
  54. };
  55. };