zerosp-ch56x-pac/pre-work/CH56Xxx-Fixed.svd

<?xml version="1.0" encoding="utf-8" standalone="no"?>
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <vendor>WCH Ltd.</vendor>                                       <!-- device vendor name -->
  <vendorID>WCH</vendorID>                                        <!-- device vendor short name -->
  <name>CH569</name>
  <version>1.0</version>
  <description>CH569 View File</description>
  <!--Bus Interface Properties-->
  <!--RISC-V is byte addressable-->

  <addressUnitBits>8</addressUnitBits>
  <!--the maximum data bit width accessible within a single transfer-->
  <width>64</width>
  <!--Register Default Properties-->
  <size>0x40</size>
  <resetValue>0x0</resetValue>
  <resetMask>0xFFFFFFFF</resetMask>
  
 <peripherals>
	<peripheral>   
		<name>SYS</name>
		<description>SYS register</description>
		<groupName>SYS</groupName>
		<baseAddress>0x40001000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_SAFE_ACCESS_SIG</name>
				<description>safe accessing sign register</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SAFE_ACC_MODE</name>
						<description>current safe accessing mode</description>
						<bitRange>[1:0]</bitRange>		
					</field>
					<field>
						<name>RB_SAFE_ACC_TIMER</name>
						<description>safe accessing timer bit mask</description>
						<bitRange>[6:4]</bitRange>		
					</field>
				</fields>
			</register>
			<register>
				<name>R8_CHIP_ID</name>
				<description>chip ID register</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x69</resetValue>
				<fields>
					<field>
						<name>R8_CHIP_ID</name>
						<description>chip ID</description>
						<bitRange>[7:0]</bitRange>		
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_SAFE_ACCESS_ID</name>
				<description>safe accessing ID register</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x02</resetValue>
				<fields>
					<field>
						<name>R8_SAFE_ACCESS_ID</name>
						<description>safe accessing ID</description>
						<bitRange>[7:0]</bitRange>		
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_WDOG_COUNT</name>
				<description>watch-dog count register</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_WDOG_COUNT</name>
						<description>watch-dog count</description>
						<bitRange>[7:0]</bitRange>		
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_GLOB_ROM_CFG</name>
				<description>flash ROM configuration register</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x80</resetValue>
				<fields>
					<field>
						<name>RB_ROM_EXT_RE</name>
						<description>enable flash ROM being read by external programmer</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_CODE_RAM_WE</name>
						<description>enable code RAM being write</description>
						<bitRange>[1:1]</bitRange>		
					</field>	
					<field>
						<name>RB_ROM_DATA_WE</name>
						<description>enable flash ROM data area being erase/write</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_ROM_CODE_WE</name>
						<description>enable flash ROM code and data area being erase or write</description>
						<bitRange>[3:3]</bitRange>		
					</field>						
					<field>
						<name>RB_ROM_CODE_OFS</name>
						<description>Config the start offset address of user code in Flash</description>
						<bitRange>[4:4]</bitRange>		
					</field>					
				</fields>
			</register>							
			<register>
				<name>R8_RST_BOOT_STAT</name>
				<description>reset status and boot/debug status</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0xC8</resetValue>
				<fields>
					<field>
						<name>RB_RESET_FLAG</name>
						<description>recent reset flag</description>
						<bitRange>[1:0]</bitRange>		
					</field>
					<field>
						<name>RB_CFG_RESET_EN</name>
						<description>manual reset input enable status</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_CFG_BOOT_EN</name>
						<description>boot-loader enable status</description>
						<bitRange>[3:3]</bitRange>		
					</field>	
					<field>
						<name>RB_CFG_DEBUG_EN</name>
						<description>debug enable status</description>
						<bitRange>[4:4]</bitRange>		
					</field>						
					<field>
						<name>RB_BOOT_LOADER</name>
						<description>indicate boot loader status</description>
						<bitRange>[5:5]</bitRange>		
					</field>					
				</fields>
			</register>
			<register>
				<name>R8_RST_WDOG_CTRL</name>
				<description>reset and watch-dog control</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SOFTWARE_RESET</name>
						<description>global software reset</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_WDOG_RST_EN</name>
						<description>enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow</description>
						<bitRange>[1:1]</bitRange>		
					</field>	
					<field>
						<name>RB_WDOG_INT_EN</name>
						<description>watch-dog interrupt enable or INT_ID_WDOG interrupt source selection: 0=software interrupt</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_WDOG_INT_FLAG</name>
						<description>watch-dog timer overflow interrupt flag</description>
						<bitRange>[3:3]</bitRange>		
					</field>											
				</fields>
			</register>
			<register>
				<name>R8_GLOB_RESET_KEEP</name>
				<description>value keeper during global reset</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_GLOB_RESET_KEEP</name>
						<description>value keeper during global reset</description>
						<bitRange>[7:0]</bitRange>		
					</field>										
				</fields>
			</register>
			<register>
				<name>R8_CLK_PLL_DIV</name>
				<description>output clock divider from PLL</description>
				<addressOffset>0x08</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x42</resetValue>
				<fields>
					<field>
						<name>R8_CLK_PLL_DIV</name>
						<description>output clock divider from PLL</description>
						<bitRange>[7:0]</bitRange>		
					</field>										
				</fields>
			</register>
			<register>
				<name>R8_CLK_CFG_CTRL</name>
				<description>clock control</description>
				<addressOffset>0x0A</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x80</resetValue>
				<fields>
					<field>
						<name>RB_CLK_PLL_SLEEP</name>
						<description>PLL sleep control</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_CLK_SEL_PLL</name>
						<description>clock source selection</description>
						<bitRange>[1:1]</bitRange>		
					</field>						
				</fields>
			</register>
			<register>
				<name>R8_CLK_MOD_AUX</name>
				<description>clock mode aux register</description>
				<addressOffset>0x0B</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_INT_125M_EN</name>
						<description>clock from USB_PHY PCLK(125MHz)</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_EXT_125M_EN</name>
						<description>clock from pin_PA[16]</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_MCO_SEL_MSK</name>
						<description>MCO output selection</description>
						<bitRange>[3:2]</bitRange>		
					</field>
					<field>
						<name>RB_MCO_EN</name>
						<description>MCO output enable</description>
						<bitRange>[4:4]</bitRange>		
					</field>					
				</fields>
			</register>			
			<register>
				<name>R8_SLP_CLK_OFF0</name>
				<description>sleep clock off control byte 0</description>
				<addressOffset>0x0C</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SLP_CLK_TMR0</name>
						<description>sleep TMR0 clock</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_TMR1</name>
						<description>sleep TMR1 clock</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_TMR2</name>
						<description>sleep TMR2 clock</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_PWMX</name>
						<description>sleep PWMX clock</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_UART0</name>
						<description>sleep UART0 clock</description>
						<bitRange>[4:4]</bitRange>		
					</field>	
					<field>
						<name>RB_SLP_CLK_UART1</name>
						<description>sleep UART1 clock</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_UART2</name>
						<description>sleep UART2 clock</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_UART3</name>
						<description>sleep UART3 clock</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_SLP_CLK_OFF1</name>
				<description>sleep clock off control byte 1</description>
				<addressOffset>0x0D</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SLP_CLK_SPI0</name>
						<description>sleep SPI0 clock</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_SPI1</name>
						<description>sleep SPI1 clock</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_EMMC</name>
						<description>sleep EMMC clock</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_HSPI</name>
						<description>sleep HSPI clock</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_USBHS</name>
						<description>sleep USBHS clock</description>
						<bitRange>[4:4]</bitRange>		
					</field>	
					<field>
						<name>RB_SLP_CLK_USBSS</name>
						<description>sleep USBSS clock</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_SERD</name>
						<description>sleep SERD clock</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_DVP</name>
						<description>sleep DVP clock</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_SLP_WAKE_CTRL</name>
				<description>wake control</description>
				<addressOffset>0x0E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SLP_USBHS_WAKE</name>
						<description>enable USBHS waking</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_USBSS_WAKE</name>
						<description>enable USBSS waking</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_ETH</name>
						<description>sleep ETH clock</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_CLK_ECDC</name>
						<description>sleep ECDC clock</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_SLP_GPIO_WAKE</name>
						<description>enable GPIO waking</description>
						<bitRange>[4:4]</bitRange>		
					</field>	
					<field>
						<name>RB_SLP_ETH_WAKE</name>
						<description>enable Eth waking</description>
						<bitRange>[5:5]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R8_SLP_POWER_CTRL</name>
				<description>power control</description>
				<addressOffset>0x0F</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SLP_USBHS_PWRDN</name>
						<description>enable USBHS power down</description>
						<bitRange>[0:0]</bitRange>		
					</field>		
				</fields>
			</register>
			<register>
				<name>R16_SERD_ANA_CFG1</name>
				<description>Serdes Analog parameter configuration1</description>
				<addressOffset>0x20</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x005A</resetValue>
				<fields>
					<field>
						<name>RB_SERD_PLL_CFG</name>
						<description>SerDes PHY internal configuration bit</description>
						<bitRange>[7:0]</bitRange>		
					</field>
					<field>
						<name>RB_SERD_30M_SEL</name>
						<description>SerDes PHY reference clock source seletion</description>
						<bitRange>[8:8]</bitRange>		
					</field>
					<field>
						<name>RB_SERD_DN_SEL</name>
						<description>Enable SerDes PHY GXM test pin</description>
						<bitRange>[9:9]</bitRange>		
					</field>					
				</fields>
			</register>
			<register>
				<name>R32_SERD_ANA_CFG2</name>
				<description>Serdes Analog parameter configuration2</description>
				<addressOffset>0x24</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00423015</resetValue>
				<fields>
					<field>
						<name>RB_SERD_TRX_CFG</name>
						<description>Tx and RX parameter setting</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R8_GPIO_INT_FLAG</name>
				<description>GPIO interrupt control</description>
				<addressOffset>0x1C</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_GPIO_PA2_IF</name>
						<description>PA2 pin interrupt flag</description>
						<bitRange>[0:0]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PA3_IF</name>
						<description>PA3 pin interrupt flag</description>
						<bitRange>[1:1]</bitRange>		
					</field>				
				</fields>				
				<fields>
					<field>
						<name>RB_GPIO_PA4_IF</name>
						<description>PA4 pin interrupt flag</description>
						<bitRange>[2:2]</bitRange>		
					</field>				
				</fields>	
				<fields>
					<field>
						<name>RB_GPIO_PB3_IF</name>
						<description>PB3 pin interrupt flag</description>
						<bitRange>[3:3]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB4_IF</name>
						<description>PB4 pin interrupt flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB11_IF</name>
						<description>PB11 pin interrupt flag</description>
						<bitRange>[5:5]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB12_IF</name>
						<description>PB12 pin interrupt flag</description>
						<bitRange>[6:6]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB15_IF</name>
						<description>PB15 pin interrupt flag</description>
						<bitRange>[7:7]</bitRange>		
					</field>				
				</fields>				
			</register>			
			<register>
				<name>R8_GPIO_INT_ENABLE</name>
				<description>GPIO interrupt enable</description>
				<addressOffset>0x1D</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_GPIO_PA2_IE</name>
						<description>PA2 pin interrupt enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PA3_IE</name>
						<description>PA3 pin interrupt enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>				
				</fields>				
				<fields>
					<field>
						<name>RB_GPIO_PA4_IE</name>
						<description>PA4 pin interrupt enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>				
				</fields>	
				<fields>
					<field>
						<name>RB_GPIO_PB3_IE</name>
						<description>PB3 pin interrupt enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB4_IE</name>
						<description>PB4 pin interrupt enable</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB11_IE</name>
						<description>PB11 pin interrupt enable</description>
						<bitRange>[5:5]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB12_IE</name>
						<description>PB12 pin interrupt enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB15_IE</name>
						<description>PB15 pin interrupt enable</description>
						<bitRange>[7:7]</bitRange>		
					</field>				
				</fields>				
			</register>			
			<register>
				<name>R8_GPIO_INT_MODE</name>
				<description>GPIO interrupt mode</description>
				<addressOffset>0x1E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_GPIO_PA2_IM</name>
						<description>PA2 pin interrupt mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PA3_IM</name>
						<description>PA3 pin interrupt mode</description>
						<bitRange>[1:1]</bitRange>		
					</field>				
				</fields>				
				<fields>
					<field>
						<name>RB_GPIO_PA4_IM</name>
						<description>PA4 pin interrupt mode</description>
						<bitRange>[2:2]</bitRange>		
					</field>				
				</fields>	
				<fields>
					<field>
						<name>RB_GPIO_PB3_IM</name>
						<description>PB3 pin interrupt mode</description>
						<bitRange>[3:3]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB4_IM</name>
						<description>PB4 pin interrupt mode</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB11_IM</name>
						<description>PB11 pin interrupt mode</description>
						<bitRange>[5:5]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB12_IM</name>
						<description>PB12 pin interrupt mode</description>
						<bitRange>[6:6]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB15_IM</name>
						<description>PB15 pin interrupt mode</description>
						<bitRange>[7:7]</bitRange>		
					</field>				
				</fields>				
			</register>	
			<register>
				<name>R8_GPIO_INT_POLAR</name>
				<description>GPIO interrupt polarity</description>
				<addressOffset>0x1F</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_GPIO_PA2_IP</name>
						<description>PA2 pin interrupt mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PA3_IP</name>
						<description>PA3 pin interrupt mode</description>
						<bitRange>[1:1]</bitRange>		
					</field>				
				</fields>				
				<fields>
					<field>
						<name>RB_GPIO_PA4_IP</name>
						<description>PA4 pin interrupt mode</description>
						<bitRange>[2:2]</bitRange>		
					</field>				
				</fields>	
				<fields>
					<field>
						<name>RB_GPIO_PB3_IP</name>
						<description>PB3 pin interrupt mode</description>
						<bitRange>[3:3]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB4_IP</name>
						<description>PB4 pin interrupt mode</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB11_IP</name>
						<description>PB11 pin interrupt mode</description>
						<bitRange>[5:5]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB12_IP</name>
						<description>PB12 pin interrupt mode</description>
						<bitRange>[6:6]</bitRange>		
					</field>				
				</fields>
				<fields>
					<field>
						<name>RB_GPIO_PB15_IP</name>
						<description>PB15 pin interrupt mode</description>
						<bitRange>[7:7]</bitRange>		
					</field>				
				</fields>				
			</register>	
			<register>
				<name>R32_PA_DIR</name>
				<description>GPIO PA I/O direction</description>
				<addressOffset>0x40</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_DIR</name>
						<description>GPIO PA I/O direction</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PA_PIN</name>
				<description>GPIO PA input</description>
				<addressOffset>0x44</addressOffset>
				<size>32</size>
				<access>read-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_PIN</name>
						<description>GPIO PA input</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PA_OUT</name>
				<description>GPIO PA output</description>
				<addressOffset>0x48</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_OUT</name>
						<description>GPIO PA output</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PA_CLR</name>
				<description>GPIO PA clear output</description>
				<addressOffset>0x4C</addressOffset>
				<size>32</size>
				<access>write-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_CLR</name>
						<description>GPIO PA clear output</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>				
			<register>
				<name>R32_PA_PU</name>
				<description>GPIO PA pullup resistance enable</description>
				<addressOffset>0x50</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_PU</name>
						<description>GPIO PA pullup resistance enable</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>					
			<register>
				<name>R32_PA_PD</name>
				<description>GPIO PA output open-drain and input pulldown resistance enable</description>
				<addressOffset>0x54</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_PD</name>
						<description>GPIO PA output open-drain and input pulldown resistance enable</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>				
			<register>
				<name>R32_PA_DRV</name>
				<description>GPIO PA driving capability</description>
				<addressOffset>0x58</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_DRV</name>
						<description>GPIO PA driving capability</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PA_SMT</name>
				<description>GPIO PA output slew rate and input schmitt trigger</description>
				<addressOffset>0x5C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PA_SMT</name>
						<description>GPIO PA output slew rate and input schmitt trigger</description>
						<bitRange>[23:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PB_DIR</name>
				<description>GPIO PB I/O direction</description>
				<addressOffset>0x60</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_DIR</name>
						<description>GPIO PB I/O direction</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PB_PIN</name>
				<description>GPIO PB input</description>
				<addressOffset>0x64</addressOffset>
				<size>32</size>
				<access>read-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_PIN</name>
						<description>GPIO PB input</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PB_OUT</name>
				<description>GPIO PB output</description>
				<addressOffset>0x68</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_OUT</name>
						<description>GPIO PB output</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PB_CLR</name>
				<description>GPIO PB clear output</description>
				<addressOffset>0x6C</addressOffset>
				<size>32</size>
				<access>write-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_CLR</name>
						<description>GPIO PB clear output</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>				
			<register>
				<name>R32_PB_PU</name>
				<description>GPIO PB pullup resistance enable</description>
				<addressOffset>0x70</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_PU</name>
						<description>GPIO PB pullup resistance enable</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>					
			<register>
				<name>R32_PB_PD</name>
				<description>GPIO PB output open-drain and input pulldown resistance enable</description>
				<addressOffset>0x74</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_PD</name>
						<description>GPIO PB output open-drain and input pulldown resistance enable</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>				
			<register>
				<name>R32_PB_DRV</name>
				<description>GPIO PB driving capability</description>
				<addressOffset>0x78</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_DRV</name>
						<description>GPIO PB driving capability</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R32_PB_SMT</name>
				<description>GPIO PB output slew rate and input schmitt trigger</description>
				<addressOffset>0x7C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_PB_SMT</name>
						<description>GPIO PB output slew rate and input schmitt trigger</description>
						<bitRange>[24:0]</bitRange>		
					</field>				
				</fields>							
			</register>	
			<register>
				<name>R8_PIN_ALTERNATE</name>
				<description>alternate pin control</description>
				<addressOffset>0x12</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_PIN_MII</name>
						<description>ETH mii interface selection</description>
						<bitRange>[0:0]</bitRange>		
					</field>	
					<field>
						<name>RB_PIN_TMR1</name>
						<description>TMR1 alternate pin enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>	
					<field>
						<name>RB_PIN_TMR2</name>
						<description>TMR2 alternate pin enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_PIN_UART0</name>
						<description>RXD0/TXD0 alternate pin enable</description>
						<bitRange>[4:4]</bitRange>		
					</field>						
				</fields>							
			</register>	
		</registers>
	</peripheral>


	<peripheral>   
		<name>TMR0</name>
		<description>TMR0 register</description>
		<groupName>TMR0</groupName>
		<baseAddress>0x40002000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_TMR0_CTRL_MOD</name>
				<description>TMR0 mode control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x02</resetValue>
				<fields>
					<field>
						<name>RB_TMR_MODE_IN</name>
						<description>timer in mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_ALL_CLEAR</name>
						<description>force clear timer FIFO and count</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_COUNT_EN</name>
						<description>timer count enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_OUT_EN</name>
						<description>timer output enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT</name>
						<description>timer PWM output polarity _ Count sub-mode</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE</name>
						<description>timer PWM repeat mode _ timer capture edge mode</description>
						<bitRange>[7:6]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_TMR0_INTER_EN</name>
				<description>TMR0 interrupt enable</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_IE_CYC_END</name>
						<description>enable interrupt for timer capture count timeout or PWM cycle end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_DATA_ACT</name>
						<description>enable interrupt for timer capture input action or PWM trigger</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_FIFO_HF</name>
						<description>enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3)</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_DMA_END</name>
						<description>enable interrupt for timer1/2 DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_FIFO_OV</name>
						<description>enable interrupt for timer FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R8_TMR0_INT_FLAG</name>
				<description>TMR0 interrupt flag</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_IF_CYC_END</name>
						<description>interrupt flag for timer capture count timeout or PWM cycle end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_DATA_ACT</name>
						<description>interrupt flag for timer capture input action or PWM trigger</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_FIFO_HF</name>
						<description>interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3)</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_DMA_END</name>
						<description>interrupt flag for timer1/2 DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_FIFO_OV</name>
						<description>interrupt flag for timer FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R8_TMR0_FIFO_COUNT</name>
				<description>TMR0 FIFO count status</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_TMR0_FIFO_COUNT</name>
						<description>TMR0 FIFO count status</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R32_TMR0_COUNT</name>
				<description>TMR0 current count</description>
				<addressOffset>0x08</addressOffset>
				<size>32</size>
				<access>read-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR0_COUNT</name>
						<description>TMR0 current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_TMR0_CNT_END</name>
				<description>TMR0 end count value, only low 26 bit</description>
				<addressOffset>0x0C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR0_COUNT</name>
						<description>TMR0 current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_TMR0_FIFO</name>
				<description>TMR0 FIFO register, only low 26 bit</description>
				<addressOffset>0x10</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR0_FIFO</name>
						<description>TMR0 FIFO current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>				
		</registers>
	</peripheral>


	<peripheral>   
		<name>TMR1</name>
		<description>TMR1 register</description>
		<groupName>TMR1</groupName>
		<baseAddress>0x40002400</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_TMR1_CTRL_MOD</name>
				<description>TMR1 mode control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x02</resetValue>
				<fields>
					<field>
						<name>RB_TMR_MODE_IN</name>
						<description>timer in mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_ALL_CLEAR</name>
						<description>force clear timer FIFO and count</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_COUNT_EN</name>
						<description>timer count enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_OUT_EN</name>
						<description>timer output enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT</name>
						<description>timer PWM output polarity _ Count sub-mode</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE</name>
						<description>timer PWM repeat mode _ timer capture edge mode</description>
						<bitRange>[7:6]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_TMR1_INTER_EN</name>
				<description>TMR1 interrupt enable</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_IE_CYC_END</name>
						<description>enable interrupt for timer capture count timeout or PWM cycle end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_DATA_ACT</name>
						<description>enable interrupt for timer capture input action or PWM trigger</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_FIFO_HF</name>
						<description>enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3)</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_DMA_END</name>
						<description>enable interrupt for timer1/2 DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_FIFO_OV</name>
						<description>enable interrupt for timer FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R8_TMR1_INT_FLAG</name>
				<description>TMR1 interrupt flag</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_IF_CYC_END</name>
						<description>interrupt flag for timer capture count timeout or PWM cycle end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_DATA_ACT</name>
						<description>interrupt flag for timer capture input action or PWM trigger</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_FIFO_HF</name>
						<description>interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3)</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_DMA_END</name>
						<description>interrupt flag for timer1_2 DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_FIFO_OV</name>
						<description>interrupt flag for timer FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R8_TMR1_FIFO_COUNT</name>
				<description>TMR1 FIFO count status</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_TMR1_FIFO_COUNT</name>
						<description>TMR FIFO count status</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R32_TMR1_COUNT</name>
				<description>TMR1 current count</description>
				<addressOffset>0x08</addressOffset>
				<size>32</size>
				<access>read-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR1_COUNT</name>
						<description>TMR current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_TMR1_CNT_END</name>
				<description>TMR1 end count value, only low 26 bit</description>
				<addressOffset>0x0C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR1_CNT_END</name>
						<description>TMR current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_TMR1_FIFO</name>
				<description>TMR1 FIFO  only low 26 bit</description>
				<addressOffset>0x10</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR1_FIFO</name>
						<description>TMR current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>		
			<register>
				<name>R8_TMR1_CTRL_DMA</name>
				<description>TMR1 DMA control</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_DMA_ENABLE</name>
						<description>timer1/2 DMA enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>	
					<field>
						<name>RB_TMR_DMA_LOOP</name>
						<description>timer1/2 DMA address loop enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R32_TMR1_DMA_NOW</name>
				<description>TMR1 DMA current address</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_TMR1_DMA_NOW</name>
						<description>TMR DMA current address</description>
						<bitRange>[17:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_TMR1_DMA_BEG</name>
				<description>TMR1 DMA begin address</description>
				<addressOffset>0x18</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_TMR1_DMA_BEG</name>
						<description>TMR1 DMA begin address</description>
						<bitRange>[17:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_TMR1_DMA_END</name>
				<description>TMR1 DMA end address</description>
				<addressOffset>0x1C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_TMR1_DMA_END</name>
						<description>TMR1 DMA end address</description>
						<bitRange>[17:0]</bitRange>		
					</field>						
				</fields>
			</register>				
		</registers>
	</peripheral>


	<peripheral>   
		<name>TMR2</name>
		<description>TMR2 register</description>
		<groupName>TMR2</groupName>
		<baseAddress>0x40002800</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_TMR2_CTRL_MOD</name>
				<description>TMR2 mode control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x02</resetValue>
				<fields>
					<field>
						<name>RB_TMR_MODE_IN</name>
						<description>timer in mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_ALL_CLEAR</name>
						<description>force clear timer FIFO and count</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_COUNT_EN</name>
						<description>timer count enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_OUT_EN</name>
						<description>timer output enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT</name>
						<description>timer PWM output polarity _ Count sub-mode</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE</name>
						<description>timer PWM repeat mode _timer capture edge mode</description>
						<bitRange>[7:6]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_TMR2_INTER_EN</name>
				<description>TMR2 interrupt enable</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_IE_CYC_END</name>
						<description>enable interrupt for timer capture count timeout or PWM cycle end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_DATA_ACT</name>
						<description>enable interrupt for timer capture input action or PWM trigger</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_FIFO_HF</name>
						<description>enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3)</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_DMA_END</name>
						<description>enable interrupt for timer1_2 DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IE_FIFO_OV</name>
						<description>enable interrupt for timer FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R8_TMR2_INT_FLAG</name>
				<description>TMR2 interrupt flag</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_IF_CYC_END</name>
						<description>interrupt flag for timer capture count timeout or PWM cycle end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_DATA_ACT</name>
						<description>interrupt flag for timer capture input action or PWM trigger</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_FIFO_HF</name>
						<description>interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3)</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_DMA_END</name>
						<description>interrupt flag for timer1_2 DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_TMR_IF_FIFO_OV</name>
						<description>interrupt flag for timer FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R8_TMR2_FIFO_COUNT</name>
				<description>TMR2 FIFO count status</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_TMR2_FIFO_COUNT</name>
						<description>TMR FIFO count status</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R32_TMR2_COUNT</name>
				<description>TMR2 current count</description>
				<addressOffset>0x08</addressOffset>
				<size>32</size>
				<access>read-only</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR2_COUNT</name>
						<description>TMR current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_TMR2_CNT_END</name>
				<description>TMR2 end count value, only low 26 bit</description>
				<addressOffset>0x0C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR2_CNT_END</name>
						<description>TMR current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_TMR2_FIFO</name>
				<description>TMR2 end count value, only low 26 bit</description>
				<addressOffset>0x10</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_TMR2_FIFO</name>
						<description>TMR current count</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>		
			<register>
				<name>R8_TMR2_CTRL_DMA</name>
				<description>TMR2 DMA control</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_TMR_DMA_ENABLE</name>
						<description>timer1_2 DMA enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>	
					<field>
						<name>RB_TMR_DMA_LOOP</name>
						<description>timer1_2 DMA address loop enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R32_TMR2_DMA_NOW</name>
				<description>TMR2 DMA current address</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_TMR2_DMA_NOW</name>
						<description>TMR DMA current address</description>
						<bitRange>[17:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_TMR2_DMA_BEG</name>
				<description>TMR2 DMA begin address</description>
				<addressOffset>0x18</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_TMR2_DMA_BEG</name>
						<description>TMR2 DMA begin address</description>
						<bitRange>[17:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_TMR2_DMA_END</name>
				<description>TMR2 DMA end address</description>
				<addressOffset>0x1C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_TMR2_DMA_END</name>
						<description>TMR2 DMA begin address</description>
						<bitRange>[17:0]</bitRange>		
					</field>						
				</fields>
			</register>				

		</registers>
	</peripheral>
	

	<peripheral>   
		<name>UART0</name>
		<description>UART0 register</description>
		<groupName>UART0</groupName>
		<baseAddress>0x40003000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_UART0_MCR</name>
				<description>UART0 modem control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_MCR_DTR</name>
						<description>UART0 control DTR</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_MCR_RTS</name>
						<description>UART0 control RTS</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_MCR_OUT1</name>
						<description>UART0 control OUT1</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_MCR_OUT2</name>
						<description>UART control OUT2</description>
						<bitRange>[3:3]</bitRange>		
					</field>						
					<field>
						<name>RB_MCR_LOOP</name>
						<description>UART0 enable local loop back</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_MCR_AU_FLOW_EN</name>
						<description>UART0 enable autoflow control</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_MCR_TNOW</name>
						<description>UART0 enable TNOW output on DTR pin</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_MCR_HALF</name>
						<description>UART0 enable half-duplex</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
									
				</fields>
			</register>		
			<register>
				<name>R8_UART0_IER</name>
				<description>UART0 interrupt enable</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_IER_RECV_RDY</name>
						<description>UART interrupt enable for receiver data ready</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IER_THR_EMPTY</name>
						<description>UART interrupt enable for THR empty</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_IER_LINE_STAT</name>
						<description>UART interrupt enable for receiver line status</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_MODEM_CHG</name>
						<description>UART0 interrupt enable for modem status change</description>
						<bitRange>[3:3]</bitRange>		
					</field>						
					<field>
						<name>RB_IER_DTR_EN</name>
						<description>UART0 DTR/TNOW output pin enable</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_IER_RTS_EN</name>
						<description>UART0 RTS output pin enable</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_IER_TXD_EN</name>
						<description>UART TXD pin enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_RESET</name>
						<description>UART software reset control, high action, auto clear</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
									
				</fields>
			</register>	
			<register>
				<name>R8_UART0_FCR</name>
				<description>UART0 FIFO control</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_FCR_FIFO_EN</name>
						<description>UART FIFO enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_RX_FIFO_CLR</name>
						<description>clear UART receiver FIFO, high action, auto clear</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_TX_FIFO_CLR</name>
						<description>clear UART transmitter FIFO, high action, auto clear</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_FCR_FIFO_TRIG</name>
						<description>UART receiver FIFO trigger level</description>
						<bitRange>[7:6]</bitRange>		
					</field>											
									
				</fields>
			</register>			
			<register>
				<name>R8_UART0_LCR</name>
				<description>UART0 line control</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_LCR_WORD_SZ</name>
						<description>UART word bit length</description>
						<bitRange>[1:0]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_STOP_BIT</name>
						<description>UART stop bit length</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_PAR_EN</name>
						<description>UART parity enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>					
					<field>
						<name>RB_LCR_PAR_MOD</name>
						<description>UART parity mode</description>
						<bitRange>[5:4]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_BREAK_EN</name>
						<description>UART break control enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_DLAB_RB_LCR_GP_BIT</name>
						<description>UART reserved bit _UART general purpose bit</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>		
			<register>
				<name>R8_UART0_IIR</name>
				<description>UART0 interrupt identification</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x01</resetValue>
				<fields>
					<field>
						<name>RB_IIR_NO_INT</name>
						<description>UART no interrupt flag</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_INT_MASK</name>
						<description>UART interrupt flag bit mask</description>
						<bitRange>[3:1]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_FIFO_ID</name>
						<description>UART FIFO enabled flag</description>
						<bitRange>[7:6]</bitRange>		
					</field>										
				</fields>
			</register>	
			<register>
				<name>R8_UART0_LSR</name>
				<description>UART0 line status</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0xC0</resetValue>
				<fields>
					<field>
						<name>RB_LSR_DATA_RDY</name>
						<description>UART receiver fifo data ready status</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_OVER_ERR</name>
						<description>UART receiver overrun error</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_PAR_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_FRAME_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[3:3]</bitRange>		
					</field>										
					<field>
						<name>RB_LSR_BREAK_ERR</name>
						<description>UART receiver break error</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_FIFO_EMP</name>
						<description>UART transmitter fifo empty status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_ALL_EMP</name>
						<description>UART transmitter all empty status</description>
						<bitRange>[6:6]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_ERR_RX_FIFO</name>
						<description>indicate error in UART receiver fifo</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>			
			<register>
				<name>R8_UART0_MSR</name>
				<description>UART0 modem status</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_MSR_CTS_CHG</name>
						<description>UART0 CTS changed status, high action</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_MSR_DSR_CHG</name>
						<description>UART0 DSR changed status, high action</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_MSR_RI_CHG</name>
						<description>UART0 RI changed status, high action</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_MSR_DCD_CHG</name>
						<description>UART0 DCD changed status, high action</description>
						<bitRange>[3:3]</bitRange>		
					</field>										
					<field>
						<name>RB_MSR_CTS</name>
						<description>UART0 CTS action status</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_MSR_DSR</name>
						<description>UART0 DSR action status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_MSR_RI</name>
						<description>UART0 RI action status</description>
						<bitRange>[6:6]</bitRange>		
					</field>	
					<field>
						<name>RB_MSR_DCD</name>
						<description>UART0 DCD action status</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART0_RBR_R8_UART0_THR</name>
				<description>UART0 receiver buffer, receiving byte _ UART0 transmitter holding, transmittal byte</description>
				<addressOffset>0x08</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART0_RBR_R8_UART0_THR</name>
						<description>UART receiver buffer, receiving byte_ UART transmitter holding, transmittal byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>					
			<register>
				<name>R8_UART0_RFC</name>
				<description>UART0 receiver FIFO count</description>
				<addressOffset>0x0A</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART_RFC</name>
						<description>UART receiver FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_UART0_TFC</name>
				<description>UART0 transmitter FIFO count</description>
				<addressOffset>0x0B</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART0_TFC</name>
						<description>UART transmitter FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R16_UART0_DL</name>
				<description>UART0 divisor latch</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_UART0_DL</name>
						<description>UART divisor latch</description>
						<bitRange>[15:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART0_DIV</name>
				<description>UART0 pre-divisor latch byte</description>
				<addressOffset>0x0E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART0_ADR</name>
						<description>UART pre-divisor latch byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART0_ADR</name>
				<description>UART0 slave address</description>
				<addressOffset>0x0F</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0xFF</resetValue>
				<fields>
					<field>
						<name>R8_UART0_ADR</name>
						<description>UART0 slave address</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>				
		</registers>
	</peripheral>	
	

	<peripheral>   
		<name>UART1</name>
		<description>UART1 register</description>
		<groupName>UART1</groupName>
		<baseAddress>0x40003400</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_UART1_MCR</name>
				<description>UART1 modem control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>									
					<field>
						<name>RB_MCR_OUT2</name>
						<description>UART1 control OUT2</description>
						<bitRange>[3:3]</bitRange>		
					</field>																																				
				</fields>
			</register>		
			<register>
				<name>R8_UART1_IER</name>
				<description>UART1 interrupt enable</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_IER_RECV_RDY</name>
						<description>UART interrupt enable for receiver data ready</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IER_THR_EMPTY</name>
						<description>UART interrupt enable for THR empty</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_IER_LINE_STAT</name>
						<description>UART interrupt enable for receiver line status</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_TXD_EN</name>
						<description>UART TXD pin enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_RESET</name>
						<description>UART software reset control, high action, auto clear</description>
						<bitRange>[7:7]</bitRange>		
					</field>											
				</fields>
			</register>	
			<register>
				<name>R8_UART1_FCR</name>
				<description>UART1 FIFO control</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_FCR_FIFO_EN</name>
						<description>UART FIFO enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_RX_FIFO_CLR</name>
						<description>clear UART receiver FIFO, high action, auto clear</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_TX_FIFO_CLR</name>
						<description>clear UART transmitter FIFO, high action, auto clear</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_FCR_FIFO_TRIG</name>
						<description>UART receiver FIFO trigger level</description>
						<bitRange>[7:6]</bitRange>		
					</field>											
									
				</fields>
			</register>			
			<register>
				<name>R8_UART1_LCR</name>
				<description>UART1 line control</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_LCR_WORD_SZ</name>
						<description>UART word bit length</description>
						<bitRange>[1:0]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_STOP_BIT</name>
						<description>UART stop bit length</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_PAR_EN</name>
						<description>UART parity enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>					
					<field>
						<name>RB_LCR_PAR_MOD</name>
						<description>UART parity mode</description>
						<bitRange>[5:4]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_BREAK_EN</name>
						<description>UART break control enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_DLAB_RB_LCR_GP_BIT</name>
						<description>UART reserved bit _ UART general purpose bit</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>		
			<register>
				<name>R8_UART1_IIR</name>
				<description>UART1 interrupt identification</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x01</resetValue>
				<fields>
					<field>
						<name>RB_IIR_NO_INT</name>
						<description>UART no interrupt flag</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_INT_MASK</name>
						<description>UART interrupt flag bit mask</description>
						<bitRange>[3:1]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_FIFO_ID</name>
						<description>UART FIFO enabled flag</description>
						<bitRange>[7:6]</bitRange>		
					</field>										
				</fields>
			</register>	
			<register>
				<name>R8_UART1_LSR</name>
				<description>UART1 line status</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0xC0</resetValue>
				<fields>
					<field>
						<name>RB_LSR_DATA_RDY</name>
						<description>UART receiver fifo data ready status</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_OVER_ERR</name>
						<description>UART receiver overrun error</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_PAR_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_FRAME_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[3:3]</bitRange>		
					</field>										
					<field>
						<name>RB_LSR_BREAK_ERR</name>
						<description>UART receiver break error</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_FIFO_EMP</name>
						<description>UART transmitter fifo empty status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_ALL_EMP</name>
						<description>UART transmitter all empty status</description>
						<bitRange>[6:6]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_ERR_RX_FIFO</name>
						<description>indicate error in UART receiver fifo</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART1_RBR_R8_UART1_THR</name>
				<description>UART1 receiver buffer, receiving byte _ UART1 transmitter holding, transmittal byte</description>
				<addressOffset>0x08</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART1_RBR_R8_UART1_THR</name>
						<description>UART receiver buffer, receiving byte_ UART transmitter holding, transmittal byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>					
			<register>
				<name>R8_UART1_RFC</name>
				<description>UART1 receiver FIFO count</description>
				<addressOffset>0x0A</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART1_RFC</name>
						<description>UART receiver FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_UART1_TFC</name>
				<description>UART1 transmitter FIFO count</description>
				<addressOffset>0x0B</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART1_TFC</name>
						<description>UART transmitter FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R16_UART1_DL</name>
				<description>UART1 divisor latch</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_UART1_DL</name>
						<description>UART divisor latch</description>
						<bitRange>[15:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART1_DIV</name>
				<description>UART1 pre-divisor latch byte</description>
				<addressOffset>0x0E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART1_DIV</name>
						<description>UART pre-divisor latch byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>				
		</registers>
	</peripheral>		
	
	
	<peripheral>   
		<name>UART2</name>
		<description>UART2 register</description>
		<groupName>UART2</groupName>
		<baseAddress>0x40003800</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_UART2_MCR</name>
				<description>UART2 modem control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>					
					<field>
						<name>RB_MCR_OUT2</name>
						<description>UART control OUT2</description>
						<bitRange>[3:3]</bitRange>		
					</field>																				
				</fields>
			</register>		
			<register>
				<name>R8_UART2_IER</name>
				<description>UART2 interrupt enable</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_IER_RECV_RDY</name>
						<description>UART interrupt enable for receiver data ready</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IER_THR_EMPTY</name>
						<description>UART interrupt enable for THR empty</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_IER_LINE_STAT</name>
						<description>UART interrupt enable for receiver line status</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_TXD_EN</name>
						<description>UART TXD pin enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_RESET</name>
						<description>UART software reset control, high action, auto clear</description>
						<bitRange>[7:7]</bitRange>		
					</field>											
				</fields>
			</register>	
			<register>
				<name>R8_UART2_FCR</name>
				<description>UART2 FIFO control</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_FCR_FIFO_EN</name>
						<description>UART FIFO enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_RX_FIFO_CLR</name>
						<description>clear UART receiver FIFO, high action, auto clear</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_TX_FIFO_CLR</name>
						<description>clear UART transmitter FIFO, high action, auto clear</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_FCR_FIFO_TRIG</name>
						<description>UART receiver FIFO trigger level</description>
						<bitRange>[7:6]</bitRange>		
					</field>											
									
				</fields>
			</register>			
			<register>
				<name>R8_UART2_LCR</name>
				<description>UART2 line control</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_LCR_WORD_SZ</name>
						<description>UART word bit length</description>
						<bitRange>[1:0]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_STOP_BIT</name>
						<description>UART stop bit length</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_PAR_EN</name>
						<description>UART parity enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>					
					<field>
						<name>RB_LCR_PAR_MOD</name>
						<description>UART parity mode</description>
						<bitRange>[5:4]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_BREAK_EN</name>
						<description>UART break control enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_DLAB_RB_LCR_GP_BIT</name>
						<description>UART reserved bit _ UART general purpose bit</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>		
			<register>
				<name>R8_UART2_IIR</name>
				<description>UART2 interrupt identification</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x01</resetValue>
				<fields>
					<field>
						<name>RB_IIR_NO_INT</name>
						<description>UART no interrupt flag</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_INT_MASK</name>
						<description>UART interrupt flag bit mask</description>
						<bitRange>[3:1]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_FIFO_ID</name>
						<description>UART FIFO enabled flag</description>
						<bitRange>[7:6]</bitRange>		
					</field>										
				</fields>
			</register>	
			<register>
				<name>R8_UART2_LSR</name>
				<description>UART2 line status</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0xC0</resetValue>
				<fields>
					<field>
						<name>RB_LSR_DATA_RDY</name>
						<description>UART receiver fifo data ready status</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_OVER_ERR</name>
						<description>UART receiver overrun error</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_PAR_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_FRAME_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[3:3]</bitRange>		
					</field>										
					<field>
						<name>RB_LSR_BREAK_ERR</name>
						<description>UART receiver break error</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_FIFO_EMP</name>
						<description>UART transmitter fifo empty status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_ALL_EMP</name>
						<description>UART transmitter all empty status</description>
						<bitRange>[6:6]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_ERR_RX_FIFO</name>
						<description>indicate error in UART receiver fifo</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART2_RBR_R8_UART2_THR</name>
				<description>UART2 receiver buffer, receiving byte _ UART2 transmitter holding, transmittal byte</description>
				<addressOffset>0x08</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART_RBR_R8_UART_THR</name>
						<description>UART receiver buffer, receiving byte_ UART transmitter holding, transmittal byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>					
			<register>
				<name>R8_UART2_RFC</name>
				<description>UART2 receiver FIFO count</description>
				<addressOffset>0x0A</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART2_RFC</name>
						<description>UART receiver FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_UART2_TFC</name>
				<description>UART2 transmitter FIFO count</description>
				<addressOffset>0x0B</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART2_TFC</name>
						<description>UART transmitter FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R16_UART2_DL</name>
				<description>UART2 divisor latch</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_UART2_DL</name>
						<description>UART divisor latch</description>
						<bitRange>[15:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART2_DIV</name>
				<description>UART2 pre-divisor latch byte</description>
				<addressOffset>0x0E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART2_DIV</name>
						<description>UART pre-divisor latch byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>			
		</registers>
	</peripheral>	


	<peripheral>   
		<name>UART3</name>
		<description>UART3 register</description>
		<groupName>UART3</groupName>
		<baseAddress>0x40003C00</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_UART3_MCR</name>
				<description>UART3 modem control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>					
					<field>
						<name>RB_MCR_OUT2</name>
						<description>UART control OUT2</description>
						<bitRange>[3:3]</bitRange>		
					</field>																				
				</fields>
			</register>		
			<register>
				<name>R8_UART3_IER</name>
				<description>UART3 interrupt enable</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_IER_RECV_RDY</name>
						<description>UART interrupt enable for receiver data ready</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IER_THR_EMPTY</name>
						<description>UART interrupt enable for THR empty</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_IER_LINE_STAT</name>
						<description>UART interrupt enable for receiver line status</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_TXD_EN</name>
						<description>UART TXD pin enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_IER_RESET</name>
						<description>UART software reset control, high action, auto clear</description>
						<bitRange>[7:7]</bitRange>		
					</field>											
				</fields>
			</register>	
			<register>
				<name>R8_UART3_FCR</name>
				<description>UART3 FIFO control</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_FCR_FIFO_EN</name>
						<description>UART FIFO enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_RX_FIFO_CLR</name>
						<description>clear UART receiver FIFO, high action, auto clear</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_FCR_TX_FIFO_CLR</name>
						<description>clear UART transmitter FIFO, high action, auto clear</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_FCR_FIFO_TRIG</name>
						<description>UART receiver FIFO trigger level</description>
						<bitRange>[7:6]</bitRange>		
					</field>																				
				</fields>
			</register>			
			<register>
				<name>R8_UART3_LCR</name>
				<description>UART3 line control</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_LCR_WORD_SZ</name>
						<description>UART word bit length</description>
						<bitRange>[1:0]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_STOP_BIT</name>
						<description>UART stop bit length</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_PAR_EN</name>
						<description>UART parity enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>					
					<field>
						<name>RB_LCR_PAR_MOD</name>
						<description>UART parity mode</description>
						<bitRange>[5:4]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_BREAK_EN</name>
						<description>UART break control enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_LCR_DLAB_RB_LCR_GP_BIT</name>
						<description>UART reserved bit and  UART general purpose bit</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>		
			<register>
				<name>R8_UART3_IIR</name>
				<description>UART3 interrupt identification</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x01</resetValue>
				<fields>
					<field>
						<name>RB_IIR_NO_INT</name>
						<description>UART no interrupt flag</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_INT_MASK</name>
						<description>UART interrupt flag bit mask</description>
						<bitRange>[3:1]</bitRange>		
					</field>
					<field>
						<name>RB_IIR_FIFO_ID</name>
						<description>UART FIFO enabled flag</description>
						<bitRange>[7:6]</bitRange>		
					</field>										
				</fields>
			</register>	
			<register>
				<name>R8_UART3_LSR</name>
				<description>UART3 line status</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0xC0</resetValue>
				<fields>
					<field>
						<name>RB_LSR_DATA_RDY</name>
						<description>UART receiver fifo data ready status</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_OVER_ERR</name>
						<description>UART receiver overrun error</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_PAR_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_FRAME_ERR</name>
						<description>UART receiver frame error</description>
						<bitRange>[3:3]</bitRange>		
					</field>										
					<field>
						<name>RB_LSR_BREAK_ERR</name>
						<description>UART receiver break error</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_FIFO_EMP</name>
						<description>UART transmitter fifo empty status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_LSR_TX_ALL_EMP</name>
						<description>UART transmitter all empty status</description>
						<bitRange>[6:6]</bitRange>		
					</field>	
					<field>
						<name>RB_LSR_ERR_RX_FIFO</name>
						<description>indicate error in UART receiver fifo</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART3_RBR_R8_UART3_THR</name>
				<description>UART3 receiver buffer, receiving byte _ UART3 transmitter holding, transmittal byte</description>
				<addressOffset>0x08</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART3_RBR_R8_UART3_THR</name>
						<description>UART receiver buffer, receiving byte _ UART transmitter holding, transmittal byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>					
			<register>
				<name>R8_UART3_RFC</name>
				<description>UART3 receiver FIFO count</description>
				<addressOffset>0x0A</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART3_RFC</name>
						<description>UART receiver FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_UART3_TFC</name>
				<description>UART3 transmitter FIFO count</description>
				<addressOffset>0x0B</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART3_TFC</name>
						<description>UART transmitter FIFO count</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R16_UART3_DL</name>
				<description>UART3 divisor latch</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_UART3_DL</name>
						<description>UART divisor latch</description>
						<bitRange>[15:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_UART3_DIV</name>
				<description>UART3 pre-divisor latch byte</description>
				<addressOffset>0x0E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_UART3_DIV</name>
						<description>UART pre-divisor latch byte</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>		
		</registers>
	</peripheral>


	<peripheral>   
		<name>SPI0</name>
		<description>SPI0 register</description>
		<groupName>SPI0</groupName>
		<baseAddress>0x40004000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_SPI0_CTRL_MOD</name>
				<description>SPI0 mode control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x02</resetValue>
				<fields>
					<field>
						<name>RB_SPI_MODE_SLAVE</name>
						<description>SPI slave mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_ALL_CLEAR</name>
						<description>force clear SPI FIFO and count</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_2WIRE_MOD</name>
						<description>SPI enable 2 wire mode</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_MST_SCK_MOD_RB_SPI_SLV_CMD_MOD</name>
						<description>SPI master clock mode _SPI slave command mode</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_FIFO_DIR</name>
						<description>SPI FIFO direction</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_SCK_OE</name>
						<description>SPI SCK output enable</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_MOSI_OE</name>
						<description>SPI MOSI output enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_MISO_OE</name>
						<description>SPI MISO output enable</description>
						<bitRange>[7:7]</bitRange>		
					</field>	
				</fields>
			</register>		
			<register>
				<name>R8_SPI0_CTRL_CFG</name>
				<description>SPI0 configuration control</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_DMA_ENABLE</name>
						<description>SPI DMA enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_DMA_LOOP</name>
						<description>SPI DMA address loop enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_AUTO_IF</name>
						<description>enable buffer or FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_BIT_ORDER</name>
						<description>SPI bit data order</description>
						<bitRange>[5:5]</bitRange>		
					</field>						
				</fields>
			</register>			
			<register>
				<name>R8_SPI0_INTER_EN</name>
				<description>SPI0 interrupt enable</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_IE_CNT_END</name>
						<description>enable interrupt for SPI total byte count end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IE_BYTE_END</name>
						<description>enable interrupt for SPI byte exchanged</description>
						<bitRange>[1:1]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_IE_FIFO_HF</name>
						<description>enable interrupt for SPI FIFO half</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IE_DMA_END</name>
						<description>enable interrupt for SPI DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_IE_FIFO_OV</name>
						<description>enable interrupt for SPI FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IE_FST_BYTE</name>
						<description>enable interrupt for SPI slave mode first byte received</description>
						<bitRange>[7:7]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R8_SPI0_CLOCK_DIV_R8_SPI0_SLAVE_PRE</name>
				<description>SPI0 master clock divisor_ SPI0 slave preset value</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x10</resetValue>
				<fields>
					<field>
						<name>R8_SPI0_CLOCK_DIV_R8_SPI0_SLAVE_PRE</name>
						<description>master clock divisor _ SPI0 slave preset value</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_SPI0_BUFFER</name>
				<description>SPI0 data buffer</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI0_BUFFER</name>
						<description>SPI data buffer</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_SPI0_RUN_FLAG</name>
				<description>SPI0 work flag</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_SLV_CMD_ACT</name>
						<description>SPI slave command flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_FIFO_READY</name>
						<description>SPI FIFO ready status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_SLV_CS_LOAD</name>
						<description>SPI slave chip-select loading status</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_SLV_SELECT</name>
						<description>SPI slave selection status</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_SPI0_INT_FLAG</name>
				<description>SPI0 interrupt flag</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_IF_CNT_END</name>
						<description>interrupt flag for SPI total byte count end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_BYTE_END</name>
						<description>interrupt flag for SPI byte exchanged</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_FIFO_HF</name>
						<description>interrupt flag for SPI FIFO half</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_DMA_END</name>
						<description>interrupt flag for SPI DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>				
					<field>
						<name>RB_SPI_IF_FIFO_OV</name>
						<description>interrupt flag for SPI FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_FREE</name>
						<description>current SPI free status</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_FST_BYTE</name>
						<description>interrupt flag for SPI slave mode first byte received</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_SPI0_FIFO_COUNT</name>
				<description>SPI0 FIFO count status</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI0_FIFO_COUNT</name>
						<description>SPI FIFO count status</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R16_SPI0_TOTAL_CNT</name>
				<description>SPI0 total byte count, only low 12 bit</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_SPI0_TOTAL_CNT</name>
						<description>SPI total byte count, only low 12 bit</description>
						<bitRange>[15:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R8_SPI0_FIFO</name>
				<description>SPI0 FIFO register</description>
				<addressOffset>0x10</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI0_FIFO</name>
						<description>SPI FIFO register</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R8_SPI0_FIFO_COUNT1</name>
				<description>SPI0 FIFO count status</description>
				<addressOffset>0x13</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI0_FIFO_COUNT1</name>
						<description>SPI FIFO count statu</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>					
			<register>
				<name>R32_SPI0_DMA_NOW</name>
				<description>SPI0 DMA current address</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R16_SPI0_DMA_NOW</name>
						<description>SPI DMA current address</description>
						<bitRange>[17:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_SPI0_DMA_BEG</name>
				<description>SPI0 DMA begin address</description>
				<addressOffset>0x18</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R16_SPI0_DMA_BEG</name>
						<description>SPI DMA begin address</description>
						<bitRange>[17:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R32_SPI0_DMA_END</name>
				<description>SPI0 DMA end address</description>
				<addressOffset>0x1C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R16_SPI0_DMA_END</name>
						<description>SPI DMA end address</description>
						<bitRange>[17:0]</bitRange>		
					</field>				
				</fields>
			</register>			
		</registers>
	</peripheral>


	<peripheral>   
		<name>SPI1</name>
		<description>SPI1 register</description>
		<groupName>SPI1</groupName>
		<baseAddress>0x40004400</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_SPI1_CTRL_MOD</name>
				<description>SPI1 mode control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x02</resetValue>
				<fields>
					<field>
						<name>RB_SPI_MODE_SLAVE</name>
						<description>SPI slave mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_ALL_CLEAR</name>
						<description>force clear SPI FIFO and count</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_2WIRE_MOD</name>
						<description>SPI enable 2 wire mode</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_MST_SCK_MOD_RB_SPI_SLV_CMD_MOD</name>
						<description>SPI master clock mode _ SPI slave command mode</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_FIFO_DIR</name>
						<description>SPI FIFO direction</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_SCK_OE</name>
						<description>SPI SCK output enable</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_MOSI_OE</name>
						<description>SPI MOSI output enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_MISO_OE</name>
						<description>SPI MISO output enable</description>
						<bitRange>[7:7]</bitRange>		
					</field>	
				</fields>
			</register>		
			<register>
				<name>R8_SPI1_CTRL_CFG</name>
				<description>SPI1 configuration control</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_DMA_ENABLE</name>
						<description>SPI DMA enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_DMA_LOOP</name>
						<description>SPI DMA address loop enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_AUTO_IF</name>
						<description>enable buffer or FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_BIT_ORDER</name>
						<description>SPI bit data order</description>
						<bitRange>[5:5]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R8_SPI1_INTER_EN</name>
				<description>SPI1 interrupt enable</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_IE_CNT_END</name>
						<description>enable interrupt for SPI total byte count end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IE_BYTE_END</name>
						<description>enable interrupt for SPI byte exchanged</description>
						<bitRange>[1:1]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_IE_FIFO_HF</name>
						<description>enable interrupt for SPI FIFO half</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IE_DMA_END</name>
						<description>enable interrupt for SPI DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>					
					<field>
						<name>RB_SPI_IE_FIFO_OV</name>
						<description>enable interrupt for SPI FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IE_FST_BYTE</name>
						<description>enable interrupt for SPI slave mode first byte received</description>
						<bitRange>[7:7]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE</name>
				<description>SPI1 master clock divisor _ SPI1 slave preset value</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x10</resetValue>
				<fields>
					<field>
						<name>R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE</name>
						<description>master clock divisor _ SPI1 slave preset value</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_SPI1_BUFFER</name>
				<description>SPI1 data buffer</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI1_BUFFER</name>
						<description>SPI data buffer</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_SPI1_RUN_FLAG</name>
				<description>SPI1 work flag</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-only</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_SLV_CMD_ACT</name>
						<description>SPI slave command flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_FIFO_READY</name>
						<description>SPI FIFO ready status</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_SLV_CS_LOAD</name>
						<description>SPI slave chip-select loading status</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_SLV_SELECT</name>
						<description>SPI slave selection status</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>				
			<register>
				<name>R8_SPI1_INT_FLAG</name>
				<description>SPI1 interrupt flag</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_SPI_IF_CNT_END</name>
						<description>interrupt flag for SPI total byte count end</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_BYTE_END</name>
						<description>interrupt flag for SPI byte exchanged</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_FIFO_HF</name>
						<description>interrupt flag for SPI FIFO half</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_DMA_END</name>
						<description>interrupt flag for SPI DMA completion</description>
						<bitRange>[3:3]</bitRange>		
					</field>				
					<field>
						<name>RB_SPI_IF_FIFO_OV</name>
						<description>interrupt flag for SPI FIFO overflow</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_FREE</name>
						<description>current SPI free status</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_SPI_IF_FST_BYTE</name>
						<description>interrupt flag for SPI slave mode first byte received</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_SPI1_FIFO_COUNT</name>
				<description>SPI1 FIFO count status</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI1_FIFO_COUNT</name>
						<description>SPI FIFO count status</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R16_SPI1_TOTAL_CNT</name>
				<description>SPI1 total byte count, only low 12 bit</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_SPI1_TOTAL_CNT</name>
						<description>SPI total byte count, only low 12 bit</description>
						<bitRange>[15:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R8_SPI1_FIFO</name>
				<description>SPI1 FIFO register</description>
				<addressOffset>0x10</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI1_FIFO</name>
						<description>SPI FIFO register</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R8_SPI1_FIFO_COUNT1</name>
				<description>SPI0 FIFO count status</description>
				<addressOffset>0x13</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_SPI1_FIFO_COUNT1</name>
						<description>SPI FIFO count statu</description>
						<bitRange>[7:0]</bitRange>		
					</field>				
				</fields>
			</register>					
			<register>
				<name>R32_SPI1_DMA_NOW</name>
				<description>SPI1 DMA current address</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_SPI1_DMA_NOW</name>
						<description>SPI DMA current address</description>
						<bitRange>[17:0]</bitRange>		
					</field>				
				</fields>
			</register>	
			<register>
				<name>R32_SPI1_DMA_BEG</name>
				<description>SPI1 DMA begin address</description>
				<addressOffset>0x18</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_SPI1_DMA_BEG</name>
						<description>SPI DMA begin address</description>
						<bitRange>[17:0]</bitRange>		
					</field>				
				</fields>
			</register>				
			<register>
				<name>R32_SPI1_DMA_END</name>
				<description>SPI1 DMA end address</description>
				<addressOffset>0x1C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>R16_SPI1_DMA_END</name>
						<description>SPI DMA end address</description>
						<bitRange>[17:0]</bitRange>		
					</field>				
				</fields>
			</register>			
		</registers>
	</peripheral>


	<peripheral>   
		<name>PWMX</name>
		<description>PWMX register</description>
		<groupName>PWMX</groupName>
		<baseAddress>0x40005000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_PWM_CTRL_MOD</name>
				<description>PWM mode control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_PWM0_OUT_EN</name>
						<description>PWM0 output enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_PWM1_OUT_EN</name>
						<description>PWM1 output enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_PWM2_OUT_EN</name>
						<description>PWM2 output enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_PWM3_OUT_EN</name>
						<description>PWM3 output enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_PWM0_POLAR</name>
						<description>PWM0 output polarity</description>
						<bitRange>[4:4]</bitRange>		
					</field>
					<field>
						<name>RB_PWM1_POLAR</name>
						<description>PWM1 output polarity</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_PWM2_POLAR</name>
						<description>PWM2 output polarity</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_PWM3_POLAR</name>
						<description>PWM3 output polarity</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>		
			<register>
				<name>R8_PWM_CTRL_CFG</name>
				<description>PWM configuration control</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_PWM_CYCLE_SEL</name>
						<description>PWM cycle selection</description>
						<bitRange>[0:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_PWM_CLOCK_DIV</name>
				<description>PWM clock divisor</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_PWM_CLOCK_DIV</name>
						<description>PWM clock divisor</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_PWM0_DATA</name>
				<description>PWM data holding</description>
				<addressOffset>0x04</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_PWM0_DATA</name>
						<description>PWM0 data holding</description>
						<bitRange>[7:0]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_PWM1_DATA</name>
				<description>PWM1 data holding</description>
				<addressOffset>0x05</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_PWM1_DATA</name>
						<description>PWM1 data holding</description>
						<bitRange>[15:8]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_PWM2_DATA</name>
				<description>PWM2 data holding</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_PWM2_DATA</name>
						<description>PWM2 data holding</description>
						<bitRange>[23:16]</bitRange>		
					</field>					
				</fields>
			</register>	
			<register>
				<name>R8_PWM3_DATA</name>
				<description>PWM3 data holding</description>
				<addressOffset>0x07</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>R8_PWM3_DATA</name>
						<description>PWM3 data holding</description>
						<bitRange>[31:24]</bitRange>		
					</field>					
				</fields>
			</register>		
		</registers>
	</peripheral>


	<peripheral>   
		<name>HSPI</name>
		<description>HSPI register</description>
		<groupName>HSPI</groupName>
		<baseAddress>0x40006000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_HSPI_CFG</name>
				<description>parallel if tx or rx cfg</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x82</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_MODE</name>
						<description>parallel if mode</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_DUALDMA</name>
						<description>parallel if dualdma mode enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_MSK_SIZE</name>
						<description>parallel if data mode</description>
						<bitRange>[3:2]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_TX_TOG_EN</name>
						<description>parallel if tx addr toggle enable</description>
						<bitRange>[5:5]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_RX_TOG_EN</name>
						<description>parallel if rx addr toggle enable</description>
						<bitRange>[6:6]</bitRange>		
					</field>	
					<field>
						<name>RB_HSPI_HW_ACK</name>
						<description>parallel if tx ack by hardware</description>
						<bitRange>[7:7]</bitRange>		
					</field>					
				</fields>
			</register>		
			<register>
				<name>R8_HSPI_CTRL</name>
				<description>parallel if tx or rx control</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x18</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_ENABLE</name>
						<description>parallel if enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_DMA_EN</name>
						<description>parallel if dma enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_SW_ACT</name>
						<description>parallel if transmit software trigger</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_ALL_CLR</name>
						<description>parallel if all clear</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_TRX_RST</name>
						<description>parallel if tx and rx logic clear, high action</description>
						<bitRange>[4:4]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R8_HSPI_INT_EN</name>
				<description>parallel if interrupt enable register</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_IE_T_DONE</name>
						<description>parallel if transmit done interrupt enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_IE_R_DONE</name>
						<description>parallel if receive done interrupt enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_IE_FIFO_OV</name>
						<description>parallel if fifo overflow interrupt enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_IE_B_DONE</name>
						<description>parallel if tx burst done interrupt enable</description>
						<bitRange>[3:3]</bitRange>		
					</field>						
				</fields>
			</register>				
			<register>
				<name>R8_HSPI_AUX</name>
				<description>parallel if aux</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_TCK_MOD</name>
						<description>parallel if tx clk polar control</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_RCK_MOD</name>
						<description>parallel if rx clk polar control</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_ACK_TX_MOD</name>
						<description>parallel if tx ack mode cfg</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_ACK_CNT_SEL</name>
						<description>delay time of parallel if send ack when receive done</description>
						<bitRange>[4:3]</bitRange>		
					</field>						
				</fields>
			</register>				
			<register>
				<name>R32_HSPI_TX_ADDR0</name>
				<description>parallel if dma tx addr0</description>
				<addressOffset>0x04</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_TX_ADDR0</name>
						<description>parallel if dma tx addr0</description>
						<bitRange>[16:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_HSPI_TX_ADDR1</name>
				<description>parallel if dma tx addr1</description>
				<addressOffset>0x08</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_TX_ADDR1</name>
						<description>parallel if dma tx addr1</description>
						<bitRange>[16:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_HSPI_RX_ADDR0</name>
				<description>parallel if dma rx addr0</description>
				<addressOffset>0x0C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_RX_ADDR0</name>
						<description>parallel if dma rx addr0</description>
						<bitRange>[16:0]</bitRange>		
					</field>						
				</fields>
			</register>			
			<register>
				<name>R32_HSPI_RX_ADDR1</name>
				<description>parallel if dma rx addr1</description>
				<addressOffset>0x10</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_RX_ADDR1</name>
						<description>parallel if dma rx addr1</description>
						<bitRange>[16:0]</bitRange>		
					</field>						
				</fields>
			</register>		
			<register>
				<name>R16_HSPI_DMA_LEN0</name>
				<description>parallel if dma length0</description>
				<addressOffset>0x14</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_DMA_LEN0</name>
						<description>parallel if dma length0</description>
						<bitRange>[11:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R16_HSPI_RX_LEN0</name>
				<description>parallel if receive length0</description>
				<addressOffset>0x16</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_RX_LEN0</name>
						<description>parallel if dma length0</description>
						<bitRange>[11:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R16_HSPI_DMA_LEN1</name>
				<description>parallel if dma length1</description>
				<addressOffset>0x18</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_DMA_LEN1</name>
						<description>parallel if dma length1</description>
						<bitRange>[11:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R16_HSPI_RX_LEN1</name>
				<description>parallel if receive length1</description>
				<addressOffset>0x1A</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_RX_LEN1</name>
						<description>parallel if dma length1</description>
						<bitRange>[11:0]</bitRange>		
					</field>						
				</fields>
			</register>				
			<register>
				<name>R16_HSPI_BURST_CFG</name>
				<description>parallel if tx burst config register</description>
				<addressOffset>0x1C</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_BURST_EN</name>
						<description>burst transmit enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_BURST_LEN</name>
						<description>burst transmit length</description>
						<bitRange>[15:8]</bitRange>		
					</field>						
				</fields>
			</register>				
			<register>
				<name>R8_HSPI_BURST_CNT</name>
				<description>parallel if tx burst count</description>
				<addressOffset>0x1E</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_BURST_CNT</name>
						<description>parallel if tx burst count</description>
						<bitRange>[7:0]</bitRange>		
					</field>						
				</fields>
			</register>		
			<register>
				<name>R32_HSPI_UDF0</name>
				<description>parallel if user defined field 0 register</description>
				<addressOffset>0x20</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_UDF0</name>
						<description>parallel if user defined field 0 register</description>
						<bitRange>[25:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R32_HSPI_UDF1</name>
				<description>parallel if user defined field 1 register</description>
				<addressOffset>0x24</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_UDF1</name>
						<description>parallel if user defined field 1 register</description>
						<bitRange>[25:0]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R8_HSPI_INT_FLAG</name>
				<description>parallel if interrupt flag</description>
				<addressOffset>0x28</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_IF_T_DONE</name>
						<description>interrupt flag for parallel if transmit done</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_HSPI_IF_R_DONE</name>
						<description>interrupt flag for parallel if receive done</description>
						<bitRange>[1:1]</bitRange>		
					</field>	
					<field>
						<name>RB_HSPI_IF_FIFO_OV</name>
						<description>interrupt flag for parallel if FIFO overflow</description>
						<bitRange>[2:2]</bitRange>		
					</field>	
					<field>
						<name>RB_HSPI_IF_B_DONE</name>
						<description>interrupt flag for parallel if tx burst done</description>
						<bitRange>[3:3]</bitRange>		
					</field>						
				</fields>
			</register>	
			<register>
				<name>R8_HSPI_RTX_STATUS</name>
				<description>parallel rtx status</description>
				<addressOffset>0x29</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_CRC_ERR</name>
						<description>CRC error occur</description>
						<bitRange>[1:1]</bitRange>		
					</field>	
					<field>
						<name>RB_HSPI_NUM_MIS</name>
						<description>rx and tx sequence number mismatch</description>
						<bitRange>[2:2]</bitRange>		
					</field>		
				</fields>
			</register>				
			<register>
				<name>R8_HSPI_TX_SC</name>
				<description>parallel TX sequence ctrl</description>
				<addressOffset>0x2A</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_TX_NUM</name>
						<description>parallel if tx sequence num</description>
						<bitRange>[3:0]</bitRange>		
					</field>	
					<field>
						<name>RB_HSPI_TX_TOG</name>
						<description>parallel if tx addr toggle flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>		
				</fields>
			</register>				
			<register>
				<name>HSPI_RX_SC</name>
				<description>parallel RX sequence ctrl</description>
				<addressOffset>0x2B</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_HSPI_RX_NUM</name>
						<description>parallel if rx sequence num</description>
						<bitRange>[3:0]</bitRange>		
					</field>	
					<field>
						<name>RB_HSPI_RX_TOG</name>
						<description>parallel if rx addr toggle flag</description>
						<bitRange>[4:4]</bitRange>		
					</field>		
				</fields>
			</register>	
		</registers>
	</peripheral>


	<peripheral>   
		<name>ECDC</name>
		<description>ECDC register</description>
		<groupName>ECDC</groupName>
		<baseAddress>0x40007000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R16_ECEC_CTRL</name>
				<description>ECED AES/SM4 register</description>
				<addressOffset>0x00</addressOffset>
				<size>16</size>
				<access>read-write</access>
                <resetValue>0x0020</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEYEX_EN</name>
						<description>enable key expansion</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_RDPERI_EN</name>
						<description>when write data to dma</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_WRPERI_EN</name>
						<description>when read data from dma</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_MODE_SEL</name>
						<description>ECDC mode select</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_CLKDIV_MASK</name>
						<description>Clock divide factor</description>
						<bitRange>[6:4]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_WRSRAM_EN</name>
						<description>module dma enable</description>
						<bitRange>[7:7]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_ALGRM_MOD</name>
						<description>Encryption and decryption algorithm mode selection</description>
						<bitRange>[8:8]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_CIPHER_MOD</name>
						<description>Block cipher mode selection</description>
						<bitRange>[9:9]</bitRange>		
					</field>					
					<field>
						<name>RB_ECDC_KLEN_MASK</name>
						<description>Key length setting</description>
						<bitRange>[11:10]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_DAT_MOD</name>
						<description>source data and result data is bit endian</description>
						<bitRange>[13:13]</bitRange>		
					</field>									
				</fields>
			</register>		
			<register>
				<name>R8_ECDC_INT_EN</name>
				<description>Interupt enable register</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_IE_EKDONE</name>
						<description>Key extension completion interrupt enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_IE_SINGLE</name>
						<description>Single encryption and decryption completion interrupt enable</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_IE_WRSRAM</name>
						<description>Memory to memory encryption and decryption completion interrupt enable</description>
						<bitRange>[2:2]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R8_ECDC_INT_FG</name>
				<description>Interupt flag register</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_IF_EKDONE</name>
						<description>Key extension completion interrupt flag</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_IF_SINGLE</name>
						<description>Single encryption and decryption completion interrupt flag</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_ECDC_IF_WRSRAM</name>
						<description>Memory to memory encryption and decryption completion interrupt flag</description>
						<bitRange>[2:2]</bitRange>		
					</field>							
				</fields>
			</register>		
			<register>
				<name>R32_ECDC_KEY_255T224</name>
				<description>User key 224-255 register</description>
				<addressOffset>0x08</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_255T224</name>
						<description>User key 224-255 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>		
			<register>
				<name>R32_ECDC_KEY_223T192</name>
				<description>User key 192-223 register</description>
				<addressOffset>0x0C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_223T192</name>
						<description>User key 192-223 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_KEY_191T160</name>
				<description>User key 160-191 register</description>
				<addressOffset>0x10</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_191T160</name>
						<description>User key 160-191 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_KEY_159T128</name>
				<description>User key 128-159 register</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_159T128</name>
						<description>User key 128-159 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_KEY_127T96</name>
				<description>User key 96-127 register</description>
				<addressOffset>0x18</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_127T96</name>
						<description>User key 96-127 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_KEY_95T64</name>
				<description>User key 64-95 register</description>
				<addressOffset>0x1C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_95T64</name>
						<description>User key 64-95 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_KEY_63T32</name>
				<description>User key 32-63 register</description>
				<addressOffset>0x20</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_63T32</name>
						<description>User key 32-63 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_KEY_31T0</name>
				<description>User key 0-31 register</description>
				<addressOffset>0x24</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_KEY_31T0</name>
						<description>User key 0-31 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_IV_127T96</name>
				<description>CTR mode count 96-127 register</description>
				<addressOffset>0x28</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_IV_127T96</name>
						<description>CTR mode count 96-127 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_IV_95T64</name>
				<description>CTR mode count 64-95 register</description>
				<addressOffset>0x2C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_IV_95T64</name>
						<description>CTR mode count 64-95 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_IV_63T32</name>
				<description>CTR mode count 32-63 register</description>
				<addressOffset>0x30</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_IV_63T32</name>
						<description>CTR mode count 32-63 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_IV_31T0</name>
				<description>CTR mode count 0-31 register</description>
				<addressOffset>0x34</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_IV_31T0</name>
						<description>CTR mode count 0-31 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_SGSD_127T96</name>
				<description>Single encryption and decryption of original data 96-127 register</description>
				<addressOffset>0x40</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGSD_127T96</name>
						<description>Single encryption and decryption of original data 96-127 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_SGSD_95T64</name>
				<description>Single encryption and decryption of original data 64-95 register</description>
				<addressOffset>0x44</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGSD_95T64</name>
						<description>Single encryption and decryption of original data 64-95 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_SGSD_63T32</name>
				<description>Single encryption and decryption of original data 32-63 register</description>
				<addressOffset>0x48</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGSD_63T32</name>
						<description>Single encryption and decryption of original data 32-63 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_SGSD_31T0</name>
				<description>Single encryption and decryption of original data 0-31 register</description>
				<addressOffset>0x4C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGSD_31T0</name>
						<description>Single encryption and decryption of original data 0-31 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>R32_ECDC_SGRT_127T96</name>
				<description>Single encryption and decryption result 96-127 register</description>
				<addressOffset>0x50</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGRT_127T96</name>
						<description>Single encryption and decryption result 96-127 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_SGRT_95T64</name>
				<description>Single encryption and decryption result 64-95 register</description>
				<addressOffset>0x54</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGRT_95T64</name>
						<description>Single encryption and decryption result 64-95  register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_SGRT_63T32</name>
				<description>Single encryption and decryption result 0-31 register</description>
				<addressOffset>0x58</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGRT_63T32</name>
						<description>Single encryption and decryption result 0-31 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>				
			<register>
				<name>RB_ECDC_SGRT_31T0</name>
				<description>Single encryption and decryption result 0-31 register</description>
				<addressOffset>0x5C</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SGRT_31T0</name>
						<description>Single encryption and decryption result 0-31 register</description>
						<bitRange>[31:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_SRAM_ADDR</name>
				<description>encryption and decryption sram start address register</description>
				<addressOffset>0x60</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SRAM_ADDR</name>
						<description>encryption and decryption sram start address register</description>
						<bitRange>[16:0]</bitRange>		
					</field>							
				</fields>
			</register>	
			<register>
				<name>R32_ECDC_SRAM_LEN</name>
				<description>encryption and decryption sram size register</description>
				<addressOffset>0x64</addressOffset>
				<size>32</size>
				<access>read-write</access>
                <resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_ECDC_SRAM_LEN</name>
						<description>encryption and decryption sram size register</description>
						<bitRange>[16:0]</bitRange>		
					</field>							
				</fields>
			</register>
		</registers>
	</peripheral>	
	
 
 	<peripheral>   
		<name>USBSS</name>
		<description>USBSS register (Please refer to subprogram library)</description>
		<groupName>USBSS</groupName>
		<baseAddress>0x40008000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>	
		<registers>
			<!-- Note by ZRY: WCH doesn't provide the register definition informations of this peripheral, maybe it was confidential -->
			<!--
			<register>

			</register>	
			-->
		</registers>	
	</peripheral>	
 
 
  	<peripheral>   
		<name>USBHS</name>
		<description>USBHS register</description>
		<groupName>USBHS</groupName>
		<baseAddress>0x40009000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_USB_CTRL</name>
				<description>USB base control</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x06</resetValue>
				<fields>
					<field>
						<name>RB_USB_DMA_EN</name>
						<description>DMA enable and DMA interrupt enable for USB</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_USB_CLR_ALL</name>
						<description>force clear FIFO and count of USB</description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_USB_RESET_SIE</name>
						<description>force reset USB SIE, need software clear</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_USB_INT_BUSY</name>
						<description>enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_DEV_PU_EN</name>
						<description>USB device enable and internal pullup resistance enable</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_USB_SPTP_MASK</name>
						<description>enable USB low speed</description>
						<bitRange>[6:5]</bitRange>
					</field>
					<field>
						<name>RB_USB_MODE</name>
						<description>enable USB host mode: 0=device mode, 1=host mode</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_UHOST_CTRL</name>
				<description>USB host control register</description>
				<addressOffset>0x01</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UH_BUS_RESET</name>
						<description>USB host send bus reset signal</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_UH_BUS_SUSPEND</name>
						<description>USB host send bus suspend signal</description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_UH_BUS_RESUME</name>
						<description>USB host suspend state and wake up device</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UH_AUTOSOF_EN</name>
						<description>Automatically generate sof packet enable control </description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>			
			<register>
				<name>R8_USB_INT_EN</name>
				<description>USB interrupt enable</description>
				<addressOffset>0x02</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_USB_IE_BUSRST_RB_USB_IE_DETECT</name>
						<description>enable interrupt for USB bus reset event for USB device mode _ enable interrupt for USB device detected event for USB host mode</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_USB_IE_TRANS</name>
						<description>enable interrupt for USB transfer completion</description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_USB_IE_SUSPEND</name>
						<description>enable interrupt for USB suspend or resume event</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_USB_IE_SOF</name>
						<description>enable interrupt for host SOF timer action for USB host mode</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_USB_IE_FIFOOV</name>
						<description>enable interrupt for FIFO overflow</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_USB_IE_SETUPACT</name>
						<description>Setup packet end interrupt</description>
						<bitRange>[5:5]</bitRange>
					</field>				
					<field>
						<name>RB_USB_IE_ISOACT</name>
						<description>Synchronous transmission received control token packet interrupt</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_USB_IE_DEV_NAK</name>
						<description>enable interrupt for NAK responded for USB device mode</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_USB_DEV_AD</name>
				<description>USB device address</description>
				<addressOffset>0x03</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>USB_ADDR_MASK</name>
						<description>bit mask for USB device address</description>
						<bitRange>[6:0]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R16_USB_FRAME_NO</name>
				<description>USB frame number register</description>
				<addressOffset>0x04</addressOffset>
				<size>16</size>
				<access>read-only</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>USB_FRAME_NO</name>
						<description>USB frame number</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_USB_SUSPEND</name>
				<description>USB suspend register</description>
				<addressOffset>0x06</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_DEV_WAKEUP</name>
						<description>Remote wake-up control bit</description>
						<bitRange>[1:1]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_USB_SPD_TYPE</name>
				<description>USB actual speed register</description>
				<addressOffset>0x08</addressOffset>
				<size>8</size>
				<access>read-only</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_USBSPEED_MASK</name>
						<description>USB actual speed</description>
						<bitRange>[1:0]</bitRange>
					</field>
				</fields>
			</register>			
			<register>
				<name>R8_USB_MIS_ST</name>
				<description>USB miscellaneous status</description>
				<addressOffset>0x09</addressOffset>
				<size>8</size>
				<access>read-only</access>
				<resetValue>0x20</resetValue>
				<fields>
					<field>
						<name>RB_USB_SPLIT_EN</name>
						<description>RO,indicate host allow SPLIT packet</description>
						<bitRange>[0:0]</bitRange>
					</field>							
					<field>
						<name>RB_USB_ATTACH</name>
						<description>RO, indicate device attached status on USB host</description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_USBBUS_SUSPEND</name>
						<description>RO, indicate USB suspend status</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_USBBUS_RESET</name>
						<description>RO, indicate USB bus reset status</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_USB_FIFO_RDY</name>
						<description>RO, indicate USB receiving FIFO ready status (not empty)</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_USB_SIE_FREE</name>
						<description>RO, indicate USB SIE free status</description>
						<bitRange>[5:5]</bitRange>
					</field>
					<field>
						<name>RB_USB_SOF_ACT</name>
						<description>RO, indicate host SOF timer action status for USB host</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_USB_SOF_PRES</name>
						<description>RO, indicate host SOF timer presage status</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_USB_INT_FG</name>
				<description>USB interrupt flag</description>
				<addressOffset>0x0A</addressOffset>
				<size>8</size>
				<access>read-write</access>				
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_USB_IF_BUSRST_RB_USB_IF_DETECT</name>
						<description>bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_USB_IF_TRANSFER</name>
						<description>USB transfer completion interrupt flag, direct bit address clear or write 1 to clear</description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_USB_IF_SUSPEND</name>
						<description>USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_USB_IF_HST_SOF</name>
						<description>host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_USB_IF_FIFOOV</name>
						<description>FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_USB_IF_SETUOACT</name>
						<description>RO, Setup transaction end interrupt flag</description>
						<bitRange>[5:5]</bitRange>
					</field>
					<field>
						<name>RB_USB_IF_ISOACT</name>
						<description>RO, Synchronous transmission received control token packet interrupt flag</description>
						<bitRange>[6:6]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_USB_INT_ST</name>
				<description>USB interrupt status</description>
				<addressOffset>0x0B</addressOffset>
				<size>8</size>
				<access>read-only</access>
				<fields>
					<field>
						<name>RB_HOST_RES_MASK_RB_DEV_ENDP_MASK</name>
						<description>RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode</description>
						<bitRange>[3:0]</bitRange>
					</field>
					<field>
						<name>RB_DEV_TOKEN_MASK</name>
						<description>RO, bit mask of current token PID code received for USB device mode</description>
						<bitRange>[5:4]</bitRange>
					</field>
					<field>
						<name>RB_USB_ST_TOGOK</name>
						<description>RO, indicate current USB transfer toggle is OK</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_USB_ST_NAK</name>
						<description>RO, indicate current USB transfer is NAK received for USB device mode</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R6_USB_RX_LEN</name>
				<description>USB receiving length</description>
				<addressOffset>0x0C</addressOffset>
				<size>16</size>
				<access>read-only</access>
				<fields>
					<field>
						<name>USB_RX_LEN</name>
						<description>length of received bytes</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_UEP4_1_MOD</name>
				<description>endpoint 1(9) 4(8,12) mode</description>
				<addressOffset>0x10</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP4_BUF_MOD</name>
						<description>buffer mode of USB endpoint 4(8,12)</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP4_TX_EN</name>
						<description>enable USB endpoint 4(8,12) transmittal (IN)</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP4_RX_EN</name>
						<description>enable USB endpoint 4(8,12) receiving (OUT)</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP1_BUF_MOD</name>
						<description>buffer mode of USB endpoint 1(9)</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_UEP1_TX_EN</name>
						<description>enable USB endpoint 1(9) transmittal (IN)</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_UEP1_RX_EN</name>
						<description>enable USB endpoint 1(9) receiving (OUT)</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R8_UEP2_3_MOD_R8_UH_EP_MOD</name>
				<description>endpoint 2(10) 3(11) mode and  USB host endpoint mode control register</description>
				<addressOffset>0x11</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP2_BUF_MOD_RB_UH_RX_EN</name>
						<description>buffer mode of USB endpoint 2(10) and  USB host receive endpoint (IN) enable</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP2_TX_EN</name>
						<description>enable USB endpoint 2(10) transmittal (IN)</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP2_RX_EN</name>
						<description>enable USB endpoint 2(10) receiving (OUT)</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP3_BUF_MOD</name>
						<description>buffer mode of USB endpoint 3(11)</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_UEP3_TX_EN_RB_UH_TX_EN</name>
						<description>enable USB endpoint 3(11) transmittal (IN) and  USB host send endpoint (SETUP/OUT) enable</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_UEP3_RX_EN</name>
						<description>enable USB endpoint 3(11) receiving (OUT)</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>        
				<name>R8_UEP5_6_MOD</name>
				<description>endpoint 5(13) 6(14) mode</description>
				<addressOffset>0x12</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP5_BUF_MOD</name>
						<description>buffer mode of USB endpoint 5(13)</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP5_TX_EN</name>
						<description>enable USB endpoint 5(13) transmittal (IN)</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP5_RX_EN</name>
						<description>enable USB endpoint 5(13) receiving (OUT)</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP6_BUF_MOD</name>
						<description>buffer mode of USB endpoint 6(14)</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_UEP6_TX_EN</name>
						<description>enable USB endpoint 6(14) transmittal (IN)</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_UEP6_RX_EN</name>
						<description>enable USB endpoint 6(14) receiving (OUT)</description>
						<bitRange>[7:7]</bitRange>
					</field>
				</fields>
			</register>
			<register>        
				<name>R8_UEP7_MOD</name>
				<description>endpoint 7(15) mode</description>
				<addressOffset>0x13</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP7_BUF_MOD</name>
						<description>buffer mode of USB endpoint 7(15)</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP7_TX_EN</name>
						<description>enable USB endpoint 7(15) transmittal (IN)</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP7_RX_EN</name>
						<description>enable USB endpoint 7(15) receiving (OUT)</description>
						<bitRange>[3:3]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_UEP0_RT_DMA</name>
				<description>endpoint 0 DMA buffer address</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP0_RT_DMA</name>
						<description>endpoint 0 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_UEP1_RX_DMA</name>
				<description>endpoint 1 DMA buffer address</description>
				<addressOffset>0x18</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP1_RX_DMA</name>
						<description>endpoint 1 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>				
			</register>
			<register>
				<name>R32_UEP2_RX_DMA_R32_UH_RX_DMA</name>
				<description>endpoint 2 DMA buffer address _ host rx endpoint buffer start address</description>
				<addressOffset>0x1C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP2_RX_DMA_UH_RX_DMA</name>
						<description>endpoint 2 DMA buffer address _ host rx endpoint buffer start address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>
			<register>
				<name>R32_UEP3_RX_DMA</name>
				<description>endpoint 3 DMA buffer address;host tx endpoint buffer high address</description>
				<addressOffset>0x20</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP3_RX_DMA</name>
						<description>endpoint 3 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>				
			</register>
			<register>
				<name>R32_UEP4_RX_DMA</name>
				<description>endpoint 4 DMA buffer address</description>
				<addressOffset>0x24</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP4_RX_DMA</name>
						<description>endpoint 4 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>
			<register>
				<name>R32_UEP5_RX_DMA</name>
				<description>endpoint 5 DMA buffer address</description>
				<addressOffset>0x28</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP5_RX_DMA</name>
						<description>endpoint 5 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>   
			<register>
				<name>R32_UEP6_RX_DMA</name>
				<description>endpoint 6 DMA buffer address</description>
				<addressOffset>0x2C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP6_RX_DMA</name>
						<description>endpoint 6 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>								
			</register>   
			<register>
				<name>R32_UEP7_RX_DMA</name>
				<description>endpoint 7 DMA buffer address</description>
				<addressOffset>0x30</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP7_RX_DMA</name>
						<description>endpoint 7 DMA buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>				
			</register>            
			<register>
				<name>R32_UEP1_TX_DMA</name>
				<description>endpoint 1 DMA TX buffer address</description>
				<addressOffset>0x34</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP1_TX_DMA</name>
						<description>endpoint 1 DMA TX buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>
			<register>
				<name>R32_UEP2_TX_DMA</name>
				<description>endpoint 2 DMA TX buffer address</description>
				<addressOffset>0x38</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP2_TX_DMA</name>
						<description>endpoint 2 DMA TX buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>			
			<register>
				<name>R32_UEP3_TX_DMA_R32_UH_TX_DMA</name>
				<description>endpoint 3 DMA TX buffer address and  host tx endpoint buffer start address</description>
				<addressOffset>0x3C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP3_TX_DMA_UH_TX_DMA</name>
						<description>endpoint 3 DMA TX buffer address and  host tx endpoint buffer start address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R32_UEP4_TX_DMA</name>
				<description>endpoint 4 DMA TX buffer address</description>
				<addressOffset>0x40</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP4_TX_DMA</name>
						<description>endpoint 4 DMA TX buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R32_UEP5_TX_DMA</name>
				<description>endpoint 5 DMA TX buffer address</description>
				<addressOffset>0x44</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP5_TX_DMA</name>
						<description>endpoint 5 DMA TX buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R32_UEP6_TX_DMA</name>
				<description>endpoint 4 DMA TX buffer address</description>
				<addressOffset>0x48</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP6_TX_DMA</name>
						<description>endpoint 6 DMA TX buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R32_UEP7_TX_DMA</name>
				<description>endpoint 7 DMA TX buffer address</description>
				<addressOffset>0x4C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>UEP7_TX_DMA</name>
						<description>endpoint 7 DMA TX buffer address</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP0_MAX_LEN</name>
				<description>endpoint 0 receive max length</description>
				<addressOffset>0x50</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP0_MAX_LEN</name>
						<description>endpoint 0 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R16_UEP1_MAX_LEN</name>
				<description>endpoint 1 receive max length</description>
				<addressOffset>0x54</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP1_MAX_LEN</name>
						<description>endpoint 1 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>					
			<register>
				<name>R16_UEP2_MAX_LEN_R16_UH_MAX_LEN</name>
				<description>endpoint 2 receive max length and USB host receive max packet length register</description>
				<addressOffset>0x58</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP2_MAX_LEN_UH_MAX_LEN</name>
						<description>endpoint 2 receive max length and  USB host receive max packet length register</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP3_MAX_LEN</name>
				<description>endpoint 3 receive max length</description>
				<addressOffset>0x5C</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP3_MAX_LEN</name>
						<description>endpoint 3 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP4_MAX_LEN</name>
				<description>endpoint 4 receive max length</description>
				<addressOffset>0x60</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP4_MAX_LEN</name>
						<description>endpoint 4 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP5_MAX_LEN</name>
				<description>endpoint 5 receive max length</description>
				<addressOffset>0x64</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP5_MAX_LEN</name>
						<description>endpoint 5 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP6_MAX_LEN</name>
				<description>endpoint 6 receive max length</description>
				<addressOffset>0x68</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP6_MAX_LEN</name>
						<description>endpoint 6 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP7_MAX_LEN</name>
				<description>endpoint 7 receive max length</description>
				<addressOffset>0x6C</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP7_MAX_LEN</name>
						<description>endpoint 7 receive max length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>	
			<register>
				<name>R16_UEP0_T_LEN</name>
				<description>endpoint 0 transmittal length</description>
				<addressOffset>0x70</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP0_T_LEN</name>
						<description>endpoint 0 transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP0_TX_CTRL</name>
				<description>endpoint 0 tx control</description>
				<addressOffset>0x72</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP0_RX_CTRL</name>
				<description>endpoint 0 rx control</description>
				<addressOffset>0x73</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R16_UEP1_T_LEN</name>
				<description>endpoint 1 transmittal length</description>
				<addressOffset>0x74</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>UEP1_T_LEN</name>
						<description>endpoint 1 transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP1_TX_CTRL</name>
				<description>endpoint 1 tx control</description>
				<addressOffset>0x76</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP1_RX_CTRL</name>
				<description>endpoint 1 rx control</description>
				<addressOffset>0x77</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R16_UEP2_T_LEN_R16_UH_EP_PID</name>
				<description>endpoint 2 transmittal length and  Set usb host token register</description>
				<addressOffset>0x78</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_UH_EPNUM_MASK</name>
						<description>The endpoint number of the target of this operation</description>
						<bitRange>[3:0]</bitRange>
					</field>
					<field>
						<name>RB_UH_TOKEN_MASK</name>
						<description>The token PID packet identification of this USB transfer transaction</description>
						<bitRange>[7:4]</bitRange>
					</field>
					<field>
						<name>UEP2_T_LEN</name>
						<description>endpoint 2 transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP2_TX_CTRL</name>
				<description>endpoint 2 tx control</description>
				<addressOffset>0x7A</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP2_RX_CTRL_R8_UH_RX_CTRL</name>
				<description>endpoint 2 rx control  and  USb host receive endpoint control register</description>
				<addressOffset>0x7B</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK_RB_UH_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT) and  Host reeiver response control bit</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO_RB_UH_RRES_NO</name>
						<description>Prepared no response and  Response control bit of host receiver</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK_RB_UH_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving and  expected data toggle flag of host receiving (IN)</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG_RB_UH_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint and  enable automatic toggle after successful receiver completion</description>
						<bitRange>[5:5]</bitRange>
					</field>
					<field>
						<name>RB_UH_RDATA_NO</name>
						<description>expect no data packet, for high speed hub in host mode</description>
						<bitRange>[6:6]</bitRange>
					</field>									
				</fields>
			</register>				
			<register>
				<name>R16_UEP3_T_LEN_R16_UH_TX_LEN</name>
				<description>endpoint 3 transmittal length and  host transmittal endpoint transmittal length</description>
				<addressOffset>0x7C</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>UEP3_T_LEN_UH_TX_LEN</name>
						<description>endpoint 3 transmittal length and  host transmittal endpoint transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP3_TX_CTRL_R8_UH_TX_CTRL</name>
				<description>endpoint 3 tx control and host transmittal endpoint control</description>
				<addressOffset>0x7E</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK_RB_UH_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN) and expected handshake response type for host transmittal (SETUP/OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO_RB_UH_TRES_NO</name>
						<description>expected no response and expected no response, 1=enable, 0=disable, for non-zero endpoint isochronous transactions</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK_RB_UH_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal and prepared data toggle flag of host transmittal (SETUP/OUT)</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG_RB_UH_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0 and enable automatic toggle after successful transfer completion</description>
						<bitRange>[5:5]</bitRange>
					</field>
					<field>
						<name>RB_UH_TDATA_NO</name>
						<description>prepared no data packet, for high speed hub in host mode</description>
						<bitRange>[6:6]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP3_RX_CTRL</name>
				<description>endpoint 3 rx control</description>
				<addressOffset>0x7F</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R16_UEP4_T_LEN_R16_UH_SPLIT_DATA</name>
				<description>endpoint 4 transmittal length and  USB host Tx SPLIT packet data</description>
				<addressOffset>0x80</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>UEP4_T_LEN_UH_SPLIT_DATA</name>
						<description>endpoint 4 transmittal length and USB host Tx SPLIT packet data</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP4_TX_CTRL</name>
				<description>endpoint 4 tx control</description>
				<addressOffset>0x82</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP4_RX_CTRL</name>
				<description>endpoint 4 rx control</description>
				<addressOffset>0x83</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R16_UEP5_T_LEN</name>
				<description>endpoint 5 transmittal length</description>
				<addressOffset>0x84</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>UEP5_T_LEN</name>
						<description>endpoint 5 transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP5_TX_CTRL</name>
				<description>endpoint 5 tx control</description>
				<addressOffset>0x86</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP5_RX_CTRL</name>
				<description>endpoint 5 rx control</description>
				<addressOffset>0x87</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R16_UEP6_T_LEN</name>
				<description>endpoint 6 transmittal length</description>
				<addressOffset>0x88</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>UEP6_T_LEN</name>
						<description>endpoint 6 transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP6_TX_CTRL</name>
				<description>endpoint 6 tx control</description>
				<addressOffset>0x8A</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP6_RX_CTRL</name>
				<description>endpoint 6 rx control</description>
				<addressOffset>0x8B</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R16_UEP7_T_LEN</name>
				<description>endpoint 7 transmittal length</description>
				<addressOffset>0x8C</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>UEP7_T_LEN</name>
						<description>endpoint 7 transmittal length</description>
						<bitRange>[15:0]</bitRange>
					</field>
				</fields>					
			</register>				
			<register>
				<name>R8_UEP7_TX_CTRL</name>
				<description>endpoint 7 tx control</description>
				<addressOffset>0x8E</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_TRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X transmittal (IN)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_TRES_NO</name>
						<description>expected no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_TOG_MASK</name>
						<description>prepared data toggle flag of USB endpoint X transmittal</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_T_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint 0</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>	
			<register>
				<name>R8_UEP7_RX_CTRL</name>
				<description>endpoint 7 rx control</description>
				<addressOffset>0x8F</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_UEP_RRES_MASK</name>
						<description> bit mask of handshake response type for USB endpoint X receiving (OUT)</description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_UEP_RRES_NO</name>
						<description>prepared no response</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_TOG_MASK</name>
						<description>expected data toggle flag of USB endpoint X receiving</description>
						<bitRange>[4:3]</bitRange>
					</field>
					<field>
						<name>RB_UEP_R_AUTOTOG</name>
						<description>enable automatic toggle after successful transfer completion on endpoint</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>				
		</registers>
	</peripheral>	
 
 
	
	
	<peripheral>   
		<name>SERDES</name>
		<description>SERDES register (Please refer to subprogram library)</description>
		<groupName>SERDES</groupName>
		<baseAddress>0x4000B000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
		<!-- Note by ZRY: WCH doesn't provide the register definition informations of this peripheral, maybe it was confidential -->
		<!--
			 <register>

			 </register>
		
		-->
		</registers>
	</peripheral>
 
 
	<!-- Note by ZRY: WCH doesn't mention it in the datasheet, I wrote this according to the example program's header file. It may be incorrect. -->
 	<peripheral>   
		<name>ETH</name>
		<description>ETH register (Please refer to subprogram library)</description>
		<groupName>ETH</groupName>
		<baseAddress>0x4000C000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R32_ETH_MACCR</name>
				<description>MAC Frame Configure Register</description>
				<addressOffset>0x0000</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACCR</name>
						<description>MAC Frame Configure Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACFFR</name>
				<description>MAC Frame Filter Configure Register</description>
				<addressOffset>0x0004</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACFFR</name>
						<description>MAC Frame Filter Configure Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACHTHR</name>
				<description>MAC Hash Table High Register</description>
				<addressOffset>0x0008</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACHTHR</name>
						<description>MAC Hash Table High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACHTLR</name>
				<description>MAC Hash Table Low Register</description>
				<addressOffset>0x000C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACHTLR</name>
						<description>MAC Hash Table Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACMIIAR</name>
				<description>MAC MII Address Register</description>
				<addressOffset>0x0010</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACMIIAR</name>
						<description>MAC MII Address Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACMIIDR</name>
				<description>MAC MII Data Register</description>
				<addressOffset>0x0014</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACMIIDR</name>
						<description>MAC MII Data Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACFCR</name>
				<description>MAC Flow-Control Register</description>
				<addressOffset>0x0018</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACFCR</name>
						<description>MAC Flow-Control Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACVLANTR</name>
				<description>MAC VLAN Tag Register</description>
				<addressOffset>0x001C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACVLANTR</name>
						<description>MAC VLAN Tag Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACRWUFFR</name>
				<description>MAC Remote Wake-Up Frame Filter Register</description>
				<addressOffset>0x0028</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACRWUFFR</name>
						<description>MAC Remote Wake-Up Frame Filter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACPMTCSR</name>
				<description>MAC PMT Control and Reset Register</description>
				<addressOffset>0x002C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACPMTCSR</name>
						<description>MAC PMT Control and Reset Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACSR</name>
				<description>MAC Interrupt Status Register</description>
				<addressOffset>0x0038</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACSR</name>
						<description>MAC Interrupt Status Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACIMR</name>
				<description>MAC Interrupt Mask Register</description>
				<addressOffset>0x003C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACIMR</name>
						<description>MAC Interrupt Mask Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA0HR</name>
				<description>MAC Address 0 High Register</description>
				<addressOffset>0x0040</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA0HR</name>
						<description>MAC Address 0 High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA0LR</name>
				<description>MAC Address 0 Low Register</description>
				<addressOffset>0x0044</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA0LR</name>
						<description>MAC Address 0 Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA1HR</name>
				<description>MAC Address 1 High Register</description>
				<addressOffset>0x0048</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA1HR</name>
						<description>MAC Address 1 High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA1LR</name>
				<description>MAC Address 1 Low Register</description>
				<addressOffset>0x004C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA1LR</name>
						<description>MAC Address 1 Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA2HR</name>
				<description>MAC Address 2 High Register</description>
				<addressOffset>0x0050</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA2HR</name>
						<description>MAC Address 2 High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA2LR</name>
				<description>MAC Address 2 Low Register</description>
				<addressOffset>0x0054</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA2LR</name>
						<description>MAC Address 2 Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA3HR</name>
				<description>MAC Address 3 High Register</description>
				<addressOffset>0x0058</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA3HR</name>
						<description>MAC Address 3 High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MACA3LR</name>
				<description>MAC Address 3 Low Register</description>
				<addressOffset>0x005C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MACA3LR</name>
						<description>MAC Address 3 Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCCR</name>
				<description>MMC Control Register</description>
				<addressOffset>0x0100</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCCR</name>
						<description>MMC Control Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCRIR</name>
				<description>MMC RX Interrupt Register</description>
				<addressOffset>0x0104</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCRIR</name>
						<description>MMC RX Interrupt Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCTIR</name>
				<description>MMC TX Interrupt Register</description>
				<addressOffset>0x0108</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCTIR</name>
						<description>MMC TX Interrupt Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCRIMR</name>
				<description>MMC RX Interrupt Mask Register</description>
				<addressOffset>0x010C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCRIMR</name>
						<description>MMC RX Interrupt Mask Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCTIMR</name>
				<description>MMC TX Interrupt Mask Register</description>
				<addressOffset>0x0144</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCTIMR</name>
						<description>MMC TX Interrupt Mask Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCTGFSCCR</name>
				<description>MMC Transmit Good Frame After Single Conflict Counter Register</description>
				<addressOffset>0x014C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCTGFSCCR</name>
						<description>MMC Transmit Good Frame After Single Conflict Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCTGFMSCCR</name>
				<description>MMC Transmit Good Frame After Multiple Conflicts Counter Register</description>
				<addressOffset>0x0150</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCTGFMSCCR</name>
						<description>MMC Transmit Good Frame After Multiple Conflicts Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCTGFCR</name>
				<description>MMC Transmit Good Frame Counter Register</description>
				<addressOffset>0x0168</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCTGFCR</name>
						<description>MMC Transmit Good Frame Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCRFCECR</name>
				<description>MMC RX Frame CRC Error Counter Register</description>
				<addressOffset>0x0194</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCRFCECR</name>
						<description>MMC RX Frame CRC Error Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCRFAECR</name>
				<description>MMC RX Frame Alignment Error Counter Register</description>
				<addressOffset>0x0198</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCRFAECR</name>
						<description>MMC RX Frame Alignment Error Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_MMCRGUFCR</name>
				<description>MMC RX Good Unicast Frame Counter Register</description>
				<addressOffset>0x01C4</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_MMCRGUFCR</name>
						<description>MMC RX Good Unicast Frame Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSCR</name>
				<description>PTP Time Stamp Control Register</description>
				<addressOffset>0x0700</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSCR</name>
						<description>PTP Time Stamp Control Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPSSIR</name>
				<description>PTP Sub Second Increment Register</description>
				<addressOffset>0x0704</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPSSIR</name>
						<description>PTP Sub Second Increment Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSHR</name>
				<description>PTP Time Stamp High Register</description>
				<addressOffset>0x0708</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSHR</name>
						<description>PTP Time Stamp High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSLR</name>
				<description>PTP Time Stamp Low Register</description>
				<addressOffset>0x070C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSLR</name>
						<description>PTP Time Stamp Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSHUR</name>
				<description>PTP Time Stamp High Update Register</description>
				<addressOffset>0x0710</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSHUR</name>
						<description>PTP Time Stamp High Update Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSLUR</name>
				<description>PTP Time Stamp Low Update Register</description>
				<addressOffset>0x0714</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSLUR</name>
						<description>PTP Time Stamp Low Update Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSAR</name>
				<description>PTP Time Stamp Accumulating Register</description>
				<addressOffset>0x0718</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSAR</name>
						<description>PTP Time Stamp Accumulating Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTTHR</name>
				<description>PTP Target Time High Register</description>
				<addressOffset>0x071C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTTHR</name>
						<description>PTP Target Time High Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTTLR</name>
				<description>PTP Target Time Low Register</description>
				<addressOffset>0x0720</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTTLR</name>
						<description>PTP Target Time Low Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_PTPTSSR</name>
				<description>PTP Time Stamp Status Register</description>
				<addressOffset>0x0724</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_PTPTSSR</name>
						<description>PTP Time Stamp Status Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMABMR</name>
				<description>DMA Bus Mode Register</description>
				<addressOffset>0x1000</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMABMR</name>
						<description>DMA Bus Mode Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMATPDR</name>
				<description>DMA TX Poll Demand Register</description>
				<addressOffset>0x1004</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMATPDR</name>
						<description>DMA TX Poll Demand Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMARPDR</name>
				<description>DMA RX Poll Demand Register</description>
				<addressOffset>0x1008</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMARPDR</name>
						<description>DMA RX Poll Demand Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMARDLAR</name>
				<description>DMA RX Description List Address Register</description>
				<addressOffset>0x100C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMARDLAR</name>
						<description>DMA RX Description List Address Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMATDLAR</name>
				<description>DMA TX Description List Address Register</description>
				<addressOffset>0x1010</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMATDLAR</name>
						<description>DMA TX Description List Address Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMASR</name>
				<description>DMA Status Register</description>
				<addressOffset>0x1014</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMASR</name>
						<description>DMA Status Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMAOMR</name>
				<description>DMA Operate Mode Register</description>
				<addressOffset>0x1018</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMAOMR</name>
						<description>DMA Operate Mode Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMAIER</name>
				<description>DMA Interrupt Enable Register</description>
				<addressOffset>0x101C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMAIER</name>
						<description>DMA Interrupt Enable Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMAMFBOCR</name>
				<description>DMA Missing Frame and Buffer Overflow Counter Register</description>
				<addressOffset>0x1020</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMAMFBOCR</name>
						<description>DMA Missing Frame and Buffer Overflow Counter Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMARSWTR</name>
				<description>DMA RX Status Watchdog Timer Register</description>
				<addressOffset>0x1024</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMARSWTR</name>
						<description>DMA RX Status Watchdog Timer Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMACHTDR</name>
				<description>DMA Current Host TX Description Register</description>
				<addressOffset>0x1048</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMACHTDR</name>
						<description>DMA Current Host TX Description Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMACHRDR</name>
				<description>DMA Current Host RX Description Register</description>
				<addressOffset>0x104C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMACHRDR</name>
						<description>DMA Current Host RX Description Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMACHTBAR</name>
				<description>DMA Current Host TX Buffer Address Register</description>
				<addressOffset>0x1050</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMACHTBAR</name>
						<description>DMA Current Host TX Buffer Address Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>
			<register>
				<name>R32_ETH_DMACHRBAR</name>
				<description>DMA Current Host RX Buffer Address Register</description>
				<addressOffset>0x1054</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_ETH_DMACHRBAR</name>
						<description>DMA Current Host RX Buffer Address Register</description>
						<bitRange>[31:0]</bitRange>		
					</field>				
				</fields>
			</register>

		</registers>
	</peripheral>
 
 
  	<peripheral>   
		<name>DVP</name>
		<description>DVP register</description>
		<groupName>DVP</groupName>
		<baseAddress>0x4000E000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>
		<registers>
			<register>
				<name>R8_DVP_CR0</name>
				<description>DVP control register0</description>
				<addressOffset>0x00</addressOffset>
				<size>8</size>
				<access>read-write</access>
                <resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_DVP_ENABLE</name>
						<description>DVP enable</description>
						<bitRange>[0:0]</bitRange>		
					</field>
					<field>
						<name>RB_DVP_V_POLAR</name>
						<description>DVP VSYNC polarity control</description>
						<bitRange>[1:1]</bitRange>		
					</field>
					<field>
						<name>RB_DVP_H_POLAR</name>
						<description>DVP HSYNC polarity control</description>
						<bitRange>[2:2]</bitRange>		
					</field>
					<field>
						<name>RB_DVP_P_POLAR</name>
						<description>DVP PCLK polarity control</description>
						<bitRange>[3:3]</bitRange>		
					</field>
					<field>
						<name>RB_DVP_MSK_DAT_MOD</name>
						<description>DVP data bit width confguration</description>
						<bitRange>[5:4]</bitRange>		
					</field>
					<field>
						<name>RB_DVP_JPEG</name>
						<description>DVP JPEG mode</description>
						<bitRange>[6:6]</bitRange>		
					</field>
					<field>
						<name>RB_DVP_RAW_CM</name>
						<description>DVP row count mode</description>
						<bitRange>[7:7]</bitRange>		
					</field>
				</fields>
			</register>		
            <register>
		        <name>R8_DVP_CR1</name>
		        <description>DVP control register1</description>
		        <addressOffset>0x01</addressOffset>
		        <size>8</size>
		        <access>read-write</access>
		        <resetValue>0x06</resetValue>
		        <fields>
			        <field>
			            <name>RB_DVP_DMA_ENABLE</name>
			            <description>DVP dma enable</description>
						<bitRange>[0:0]</bitRange>	
			        </field>
				    <field>
			            <name>RB_DVP_ALL_CLR</name>
			            <description>DVP all clear, high action</description>
						<bitRange>[1:1]</bitRange>	
			        </field>
				    <field>
			            <name>RB_DVP_RCV_CLR</name>
			            <description>DVP receive logic clear, high action</description>
						<bitRange>[2:2]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_BUF_TOG</name>
			            <description>DVP bug toggle by software</description>
						<bitRange>[3:3]</bitRange>	
			        </field>
		        </fields>
		    </register>
            <register>
		        <name>R8_DVP_INT_EN</name>
		        <description>DVP interrupt enable register</description>
		        <addressOffset>0x02</addressOffset>
		        <size>8</size>
		        <access>read-write</access>
		        <resetValue>0x00</resetValue>
		        <fields>
			        <field>
			            <name>RB_DVP_IE_STR_FRM</name>
			            <description>DVP frame start interrupt enable</description>
						<bitRange>[0:0]</bitRange>	
			        </field>
				    <field>
			            <name>RB_DVP_IE_ROW_DONE</name>
			            <description>DVP row received done interrupt enable</description>
						<bitRange>[1:1]</bitRange>	
			        </field>
				    <field>
			            <name>RB_DVP_IE_FRM_DONE</name>
			            <description>DVP frame received done interrupt enable</description>
						<bitRange>[2:2]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_IE_FIFO_OV</name>
			            <description>DVP receive fifo overflow interrupt enable	</description>
						<bitRange>[3:3]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_IE_STP_FRM</name>
			            <description>DVP frame stop interrupt enable	</description>
						<bitRange>[4:4]</bitRange>	
			        </field>
		        </fields>
		    </register>			
            <register>
		        <name>R16_DVP_ROW_NUM</name>
		        <description>DVP row number of a frame indicator register</description>
		        <addressOffset>0x04</addressOffset>
		        <size>16</size>
		        <access>read-write</access>
		        <resetValue>0x0000</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_ROW_NUM</name>
			            <description>the number of rows contained in a frame of image data</description>
						<bitRange>[15:0]</bitRange>	
			        </field>
		        </fields>
		    </register>	
			<register>
		        <name>R16_DVP_COL_NUM</name>
		        <description>DVP row number of a frame indicator register</description>
		        <addressOffset>0x06</addressOffset>
		        <size>16</size>
		        <access>read-write</access>
		        <resetValue>0x0000</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_COL_NUM</name>
			            <description>the number of PCLK cyccles contained in a row of data in RGB mode</description>
						<bitRange>[15:0]</bitRange>	
			        </field>
		        </fields>
		    </register>	
			<register>
		        <name>R32_DVP_DMA_BUF0</name>
		        <description> DVP dma buffer0 addr</description>
		        <addressOffset>0x08</addressOffset>
		        <size>32</size>
		        <access>read-write</access>
		        <resetValue>0x00000000</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_DMA_BUF0</name>
			            <description>the receiving address 0 of DMA</description>
						<bitRange>[16:0]</bitRange>	
			        </field>
		        </fields>
		    </register>
			<register>
		        <name>R32_DVP_DMA_BUF1</name>
		        <description> DVP dma buffer1 addr</description>
		        <addressOffset>0x0c</addressOffset>
		        <size>32</size>
		        <access>read-write</access>
		        <resetValue>0x00000000</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_DMA_BUF1</name>
			            <description>the receiving address1 of DMA</description>
						<bitRange>[16:0]</bitRange>	
			        </field>
		        </fields>
		    </register>
			<register>
		        <name>R8_DVP_INT_FLAG</name>
		        <description> DVP interrupt flag register</description>
		        <addressOffset>0x10</addressOffset>
		        <size>32</size>
		        <access>read-write</access>
		        <resetValue>0x00</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_IF_STR_FRM</name>
			            <description>interrupt flag for DVP frame start</description>
						<bitRange>[0:0]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_IF_ROW_DONE</name>
			            <description>interrupt flag for DVP row receive done</description>
						<bitRange>[1:1]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_IF_FRM_DONE</name>
			            <description>interrupt flag for DVP frame receive done</description>
						<bitRange>[2:2]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_IF_FIFO_OV</name>
			            <description>interrupt flag for DVP receive fifo overflow</description>
						<bitRange>[3:3]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_IF_STP_FRM</name>
			            <description>interrupt flag for DVP frame stop</description>
						<bitRange>[4:4]</bitRange>	
			        </field>
		        </fields>
		    </register>
			<register>
		        <name>R8_DVP_FIFO_ST</name>
		        <description> DVP receive fifo status</description>
		        <addressOffset>0x11</addressOffset>
		        <size>8</size>
		        <access>read-only</access>
		        <resetValue>0x00</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_FIFO_RDY</name>
			            <description>DVP receive fifo ready</description>
						<bitRange>[0:0]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_FIFO_FULL</name>
			            <description>DVP receive fifo full</description>
						<bitRange>[1:1]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_FIFO_OV</name>
			            <description>DVP receive fifo overflow</description>
						<bitRange>[2:2]</bitRange>	
			        </field>
					<field>
			            <name>RB_DVP_MSK_FIFO_CNT</name>
			            <description>DVP receive fifo count</description>
						<bitRange>[6:4]</bitRange>	
			        </field>
		        </fields>
		    </register>	
			<register>
		        <name>R16_DVP_ROW_CNT</name>
		        <description> DVP row count value</description>
		        <addressOffset>0x14</addressOffset>
		        <size>16</size>
		        <access>read-only</access>
		        <resetValue>0x0000</resetValue>
		        <fields>
					<field>
			            <name>RB_DVP_ROW_CNT</name>
			            <description>DVP receive fifo full</description>
						<bitRange>[15:0]</bitRange>	
			        </field>
		        </fields>
		    </register>
			<register> 
		        <name>R16_DVP_COL_CNT</name>
		        <description> DVP col count value</description>
		        <addressOffset>0x16</addressOffset>
		        <size>16</size>
		        <access>read-only</access>
		        <resetValue>0x0000</resetValue>
		        <fields>
				    <field>
			            <name>RB_DVP_COL_CNT</name>
			            <description>DVP receive fifo ready</description>
						<bitRange>[15:0]</bitRange>	
			        </field>
		        </fields>
		    </register>													
		</registers>
	</peripheral>
 
 
	<peripheral>
	    <name>PFIC</name>
	    <description>Program Fast Interrupt Controller</description>
	    <groupName>PFIC</groupName>
	    <baseAddress>0xE000E000</baseAddress>
	    <addressBlock>
		   <offset>0x0</offset>
		   <size>0x1000</size>					
		   <usage>registers</usage>
	    </addressBlock>
	    <registers>
		    <register>
		        <name>R32_PFIC_ISR1</name>
		        <displayName>ISR1</displayName>
		        <description>Interrupt Status Register</description>
		        <addressOffset>0x0</addressOffset>
		        <size>0x20</size>
		        <access>read-only</access>
		        <resetValue>0x00000000</resetValue>
		        <fields>		   
			       <field>
			           <name>INTSTA</name>
			           <description>Interrupt ID Status</description>
			           <bitOffset>12</bitOffset>
			           <bitWidth>20</bitWidth>
			        </field>
		        </fields>
		    </register>
		    <register>
		        <name>R32_PFIC_ISR2</name>
		  		<displayName>ISR2</displayName>
		  		<description>Interrupt Status Register</description>
		 		<addressOffset>0x04</addressOffset>
		  		<size>0x20</size>
		  		<access>read-only</access>
		  		<resetValue>0x00000000</resetValue>
		  		<fields>
			        <field>
			            <name>INTENSTA</name>
			            <description>Interrupt ID Status</description>
			            <bitOffset>0</bitOffset>
			            <bitWidth>28</bitWidth>
			        </field>
		        </fields>
		    </register>
		    <register>
		        <name>R32_PFIC_IPR1</name>
		        <displayName>IPR1</displayName>
		  		<description>Interrupt Pending Register</description>
		  		<addressOffset>0x20</addressOffset>
		  		<size>0x20</size>
		  		<access>read-only</access>
		  		<resetValue>0x00000000</resetValue>
		  		<fields>
					<field>
			  			<name>PENDSTA</name>
			  			<description>PENDSTA</description>
			  			<bitOffset>12</bitOffset>
			  			<bitWidth>20</bitWidth>
					</field>
		  		</fields>
			</register>
			<register>
		 	 	<name>R32_PFIC_IPR2</name>
		  		<displayName>IPR2</displayName>
		  		<description>Interrupt Pending Register</description>
		 	 	<addressOffset>0x24</addressOffset>
		  		<size>0x20</size>
		  		<access>read-only</access>
		  		<resetValue>0x00000000</resetValue>
		  		<fields>
					<field>
			  			<name>PENDSTA</name>
			  			<description>PENDSTA</description>
			  			<bitOffset>0</bitOffset>
			  			<bitWidth>28</bitWidth>
					</field>
		  		</fields>
			</register>
			<register>
		  		<name>R32_PFIC_ITHRESDR</name>
		  		<displayName>ITHRESDR</displayName>
		  		<description>Interrupt Priority Register</description>
		  		<addressOffset>0x40</addressOffset>
		  		<size>0x20</size>
		  		<access>read-write</access>
		  		<resetValue>0x00000000</resetValue>
		  		<fields>
					<field>
			  			<name>THRESHOLD</name>
			  			<description>THRESHOLD</description>
			  			<bitOffset>0</bitOffset>
			  			<bitWidth>8</bitWidth>
					</field>
		  		</fields>
			</register>
			<register>
		  		<name>R32_PFIC_FIBADDRR</name>
		  		<displayName>FIBADDRR</displayName>
		  		<description>Interrupt Fast Address Register</description>
		  		<addressOffset>0x44</addressOffset>
		  		<size>0x20</size>
		  		<access>read-write</access>
		  		<resetValue>0x00000000</resetValue>
		  		<fields>
					<field>
			  			<name>BASEADDR</name>
			  			<description>BASEADDR</description>
			 	 		<bitOffset>28</bitOffset>
			  			<bitWidth>4</bitWidth>
					</field>
		  		</fields>
			</register>
			<register>
		  		<name>R32_PFIC_CFGR</name>
		  		<displayName>CFGR</displayName>
		  		<description>Interrupt Config Register</description>
		  		<addressOffset>0x48</addressOffset>
		  		<size>0x20</size>        
		  		<resetValue>0x00000000</resetValue>
		  		<fields>
					<field>
			  			<name>HWSTKCTRL</name>
			  			<description>HWSTKCTRL</description>
			   			<access>read-write</access>
			  			<bitOffset>0</bitOffset>
			  			<bitWidth>1</bitWidth>
					</field>
				    <field>
						<name>NESTCTRL</name>
						<description>NESTCTRL</description>
						<access>read-write</access>
						<bitOffset>1</bitOffset>
						<bitWidth>1</bitWidth>
				   </field>
				   <field>
						<name>NMISET</name>
						<description>NMISET</description>
						<access>write-only</access>
						<bitOffset>2</bitOffset>
						<bitWidth>1</bitWidth>
				    </field>
				    <field>
						<name>NMIRESET</name>
						<description>NMIRESET</description>
						<access>write-only</access>
						<bitOffset>3</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>EXCSET</name>
						<description>EXCSET</description>
						<access>write-only</access>
						<bitOffset>4</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>EXCRESET</name>
						<description>EXCRESET</description>
						<access>write-only</access>
						<bitOffset>5</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>PFICRESET</name>
						<description>PFICRSET</description>
						<access>write-only</access>
						<bitOffset>6</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>SYSRESET</name>
						<description>SYSRESET</description>
						<access>write-only</access>
						<bitOffset>7</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>KEYCODE</name>
						<description>KEYCODE</description>
						<access>write-only</access>
						<bitOffset>16</bitOffset>
						<bitWidth>16</bitWidth>
					</field>
		   		</fields>
		</register>
		<register>
			<name>R32_PFIC_GISR</name>
			<displayName>GISR</displayName>
			<description>Interrupt Global Register</description>
			<addressOffset>0x4C</addressOffset>
			<size>0x20</size>
			<access>read-only</access>
			<resetValue>0x00000000</resetValue>
			   <fields>
					<field>
						<name>NESTSTA</name>
						<description>NESTSTA</description>
						<bitOffset>0</bitOffset>
						<bitWidth>8</bitWidth>
				    </field>
					<field>
					<name>GACTSTA</name>
						<description>GACTSTA</description>
						<bitOffset>8</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>GPENDSTA</name>
						<description>GPENDSTA</description>
						<bitOffset>9</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
		  		</fields>
		</register>
		<register>
		  	    <name>R32_PFIC_FIFOADDRR0</name>
		 	    <displayName>FIFOADDRR0</displayName>
		 	    <description>Interrupt 0 address Register</description>
		 	    <addressOffset>0x60</addressOffset>
		     	<size>0x20</size>
		 	    <access>read-write</access>
		 	    <resetValue>0x00000000</resetValue>
		  		<fields>
					<field>
						<name>OFFADDR0</name>
						<description>OFFADDR0</description>
						<bitOffset>0</bitOffset>
						<bitWidth>24</bitWidth>
					</field>
			        <field>
						<name>IRQID0</name>
						<description>IRQID0</description>
						<bitOffset>24</bitOffset>
						<bitWidth>8</bitWidth>
					</field>
		  		</fields>
		</register>
		<register>
			 <name>R32_PFIC_FIFOADDRR1</name>
			 <displayName>FIFOADDRR1</displayName>
			 <description>Interrupt 1 address Register</description>
			 <addressOffset>0x64</addressOffset>
			 <size>0x20</size>
			 <access>read-write</access>
			 <resetValue>0x00000000</resetValue>
		     <fields>
			    <field>
					<name>OFFADDR1</name>
					<description>OFFADDR1</description>
					<bitOffset>0</bitOffset>
					<bitWidth>24</bitWidth>
			    </field>
			    <field>
					<name>IRQID1</name>
					<description>IRQID1</description>
					<bitOffset>24</bitOffset>
					<bitWidth>8</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_FIFOADDRR2</name>
			<displayName>FIFOADDRR2</displayName>
			<description>Interrupt 2 address Register</description>
			<addressOffset>0x68</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		    <fields>
				<field>
					<name>OFFADDR2</name>
					<description>OFFADDR2</description>
					<bitOffset>0</bitOffset>
					<bitWidth>24</bitWidth>
				</field>
				<field>
					<name>IRQID2</name>
					<description>IRQID2</description>
					<bitOffset>24</bitOffset>
					<bitWidth>8</bitWidth>
				</field>
		    </fields>
		</register>
		<register>
			<name>R32_PFIC_FIFOADDRR3</name>
			<displayName>FIFOADDRR3</displayName>
			<description>Interrupt 3 address Register</description>
			<addressOffset>0x6C</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		    <fields>
				<field>
					<name>OFFADDR3</name>
					<description>OFFADDR3</description>
					<bitOffset>0</bitOffset>
					<bitWidth>24</bitWidth>
				</field>
			    <field>
					<name>IRQID3</name>
					<description>IRQID3</description>
					<bitOffset>24</bitOffset>
					<bitWidth>8</bitWidth>
			    </field>
		    </fields>
		</register>
		<register>
			<name>R32_PFIC_IENR1</name>
			<displayName>IENR1</displayName>
			<description>Interrupt Setting Register</description>
			<addressOffset>0x100</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		    <fields>
				<field>
					<name>INTEN</name>
					<description>INTEN</description>
					<bitOffset>12</bitOffset>
					<bitWidth>20</bitWidth>
				</field>
		    </fields>
		</register>
		<register>
			<name>R32_PFIC_IENR2</name>
			<displayName>IENR2</displayName>
			<description>Interrupt Setting Register</description>
			<addressOffset>0x104</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		  	<fields>
				<field>
					<name>INTEN</name>
					<description>INTEN</description>
					<bitOffset>0</bitOffset>
					<bitWidth>28</bitWidth>
				</field>
		    </fields>
		</register>
		 <register>
			<name>R32_PFIC_IRER1</name>
			<displayName>IRER1</displayName>
			<description>Interrupt Clear Register</description>
			<addressOffset>0x180</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>INTRESET</name>
					<description>INTRESET</description>
					<bitOffset>12</bitOffset>
					<bitWidth>20</bitWidth>
				</field>
			</fields>
		</register>
		<register>
			<name>R32_PFIC_IRER2</name>
			<displayName>IRER2</displayName>
			<description>Interrupt Clear Register</description>
			<addressOffset>0x184</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>INTRESET</name>
					<description>INTRESET</description>
					<bitOffset>0</bitOffset>
					<bitWidth>28</bitWidth>
				</field>
		    </fields>
		</register>
		<register>
			<name>R32_PFIC_IPSR1</name>
			<displayName>IPSR1</displayName>
			<description>Interrupt Pending Register</description>
			<addressOffset>0x200</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>PENDSET</name>
					<description>PENDSET</description>
					<bitOffset>12</bitOffset>
					<bitWidth>20</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IPSR2</name>
			<displayName>IPSR2</displayName>
			<description>Interrupt Pending Register</description>
			<addressOffset>0x204</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>PENDSET</name>
					<description>PENDSET</description>
					<bitOffset>0</bitOffset>
					<bitWidth>28</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IPRR1</name>
			<displayName>IPRR1</displayName>
			<description>Interrupt Pending Clear Register</description>
			<addressOffset>0x280</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>PENDRESET</name>
					<description>PENDRESET</description>
					<bitOffset>12</bitOffset>
					<bitWidth>20</bitWidth>
				</field>
		  </fields>
		</register>
		<register>
			<name>R32_PFIC_IPRR2</name>
			<displayName>IPRR2</displayName>
			<description>Interrupt Pending Clear Register</description>
			<addressOffset>0x284</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		  	<fields>
				<field>
					<name>PENDRESET</name>
					<description>PENDRESET</description>
					<bitOffset>0</bitOffset>
					<bitWidth>28</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IACTR1</name>
			<displayName>IACTR1</displayName>
			<description>Interrupt ACTIVE Register</description>
			<addressOffset>0x300</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		  	<fields>
				<field>
					<name>IACTS</name>
					<description>IACTS</description>
					<bitOffset>12</bitOffset>
					<bitWidth>20</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IACTR2</name>
			<displayName>IACTR2</displayName>
			<description>Interrupt ACTIVE Register</description>
			<addressOffset>0x304</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		  	<fields>
				<field>
					<name>IACTS</name>
					<description>IACTS</description>
					<bitOffset>0</bitOffset>
					<bitWidth>28</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IPRIOR0</name>
			<displayName>IPRIOR0</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x400</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
		  	<fields>
				<field>
					<name>IPRIOR0</name>
					<description>IPRIOR0</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IPRIOR1</name>
			<displayName>IPRIOR1</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x420</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR1</name>
					<description>IPRIOR1</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>
		<register>
			<name>R32_PFIC_IPRIOR2</name>
			<displayName>IPRIOR2</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x440</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR2</name>
					<description>IPRIOR2</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>
		<register>
			<name>R32_PFIC_IPRIOR3</name>
			<displayName>IPRIOR3</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x460</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR3</name>
					<description>IPRIOR3</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		 	</fields>
		</register>		
		<register>
			<name>R32_PFIC_IPRIOR4</name>
			<displayName>IPRIOR4</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x480</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR4</name>
					<description>IPRIOR4</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR5</name>
			<displayName>IPRIOR5</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x4A0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR5</name>
					<description>IPRIOR5</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR6</name>
			<displayName>IPRIOR6</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x4C0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR6</name>
					<description>IPRIOR6</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR7</name>
			<displayName>IPRIOR7</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x4E0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR7</name>
					<description>IPRIOR7</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR8</name>
			<displayName>IPRIOR8</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x500</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR8</name>
					<description>IPRIOR8</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR9</name>
			<displayName>IPRIOR9</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x520</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR9</name>
					<description>IPRIOR9</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR10</name>
			<displayName>IPRIOR10</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x540</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR10</name>
					<description>IPRIOR10</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR11</name>
			<displayName>IPRIOR11</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x560</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR11</name>
					<description>IPRIOR11</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR12</name>
			<displayName>IPRIOR12</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x580</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR12</name>
					<description>IPRIOR12</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR13</name>
			<displayName>IPRIOR13</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x5A0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR13</name>
					<description>IPRIOR13</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR14</name>
			<displayName>IPRIOR14</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x5C0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR14</name>
					<description>IPRIOR14</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR15</name>
			<displayName>IPRIOR15</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x5E0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR15</name>
					<description>IPRIOR15</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR16</name>
			<displayName>IPRIOR16</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x600</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR16</name>
					<description>IPRIOR16</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR17</name>
			<displayName>IPRIOR17</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x620</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR17</name>
					<description>IPRIOR17</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR18</name>
			<displayName>IPRIOR18</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x640</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR18</name>
					<description>IPRIOR18</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR19</name>
			<displayName>IPRIOR19</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x660</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR19</name>
					<description>IPRIOR19</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR20</name>
			<displayName>IPRIOR20</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x680</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR20</name>
					<description>IPRIOR20</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR21</name>
			<displayName>IPRIOR21</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x6A0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR21</name>
					<description>IPRIOR21</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR22</name>
			<displayName>IPRIOR22</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x6C0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR22</name>
					<description>IPRIOR22</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR23</name>
			<displayName>IPRIOR23</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x6E0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR23</name>
					<description>IPRIOR23</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR24</name>
			<displayName>IPRIOR24</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x700</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR24</name>
					<description>IPRIOR24</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR25</name>
			<displayName>IPRIOR25</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x720</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR25</name>
					<description>IPRIOR25</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR26</name>
			<displayName>IPRIOR26</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x740</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR26</name>
					<description>IPRIOR26</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR27</name>
			<displayName>IPRIOR27</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x760</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR27</name>
					<description>IPRIOR27</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR28</name>
			<displayName>IPRIOR28</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x780</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR28</name>
					<description>IPRIOR28</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR29</name>
			<displayName>IPRIOR29</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x7A0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR29</name>
					<description>IPRIOR29</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR30</name>
			<displayName>IPRIOR30</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x7C0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR30</name>
					<description>IPRIOR30</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR31</name>
			<displayName>IPRIOR31</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x7E0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR31</name>
					<description>IPRIOR31</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR32</name>
			<displayName>IPRIOR32</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x800</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR32</name>
					<description>IPRIOR32</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR33</name>
			<displayName>IPRIOR33</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x820</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR33</name>
					<description>IPRIOR33</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR34</name>
			<displayName>IPRIOR34</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x840</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR34</name>
					<description>IPRIOR34</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR35</name>
			<displayName>IPRIOR35</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x860</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR35</name>
					<description>IPRIOR35</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR36</name>
			<displayName>IPRIOR36</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x880</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR36</name>
					<description>IPRIOR36</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR37</name>
			<displayName>IPRIOR37</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x8A0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR37</name>
					<description>IPRIOR37</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR38</name>
			<displayName>IPRIOR38</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x8C0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR38</name>
					<description>IPRIOR38</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR39</name>
			<displayName>IPRIOR39</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x8E0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR39</name>
					<description>IPRIOR39</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR40</name>
			<displayName>IPRIOR40</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x900</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR40</name>
					<description>IPRIOR40</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR41</name>
			<displayName>IPRIOR41</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x920</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR41</name>
					<description>IPRIOR41</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR42</name>
			<displayName>IPRIOR42</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x940</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR42</name>
					<description>IPRIOR42</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR43</name>
			<displayName>IPRIOR43</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x960</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR43</name>
					<description>IPRIOR43</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR44</name>
			<displayName>IPRIOR44</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x980</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR44</name>
					<description>IPRIOR44</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR45</name>
			<displayName>IPRIOR45</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x9A0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR45</name>
					<description>IPRIOR45</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR46</name>
			<displayName>IPRIOR46</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x9C0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR46</name>
					<description>IPRIOR46</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR47</name>
			<displayName>IPRIOR47</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0x9E0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR47</name>
					<description>IPRIOR47</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR48</name>
			<displayName>IPRIOR48</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xA00</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR48</name>
					<description>IPRIOR48</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR49</name>
			<displayName>IPRIOR49</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xA20</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR49</name>
					<description>IPRIOR49</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR50</name>
			<displayName>IPRIOR50</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xA40</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR50</name>
					<description>IPRIOR50</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR51</name>
			<displayName>IPRIOR51</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xA60</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR51</name>
					<description>IPRIOR51</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR52</name>
			<displayName>IPRIOR52</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xA80</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR52</name>
					<description>IPRIOR52</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR53</name>
			<displayName>IPRIOR53</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xAA0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR53</name>
					<description>IPRIOR53</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR54</name>
			<displayName>IPRIOR54</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xAD0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR54</name>
					<description>IPRIOR54</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR55</name>
			<displayName>IPRIOR55</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xAE0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR55</name>
					<description>IPRIOR55</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR56</name>
			<displayName>IPRIOR56</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xB00</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR56</name>
					<description>IPRIOR56</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR57</name>
			<displayName>IPRIOR57</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xB20</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR57</name>
					<description>IPRIOR57</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR58</name>
			<displayName>IPRIOR58</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xB40</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR58</name>
					<description>IPRIOR58</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR59</name>
			<displayName>IPRIOR59</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xB60</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR59</name>
					<description>IPRIOR59</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR60</name>
			<displayName>IPRIOR60</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xB80</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR60</name>
					<description>IPRIOR60</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR61</name>
			<displayName>IPRIOR61</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xBA0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR61</name>
					<description>IPRIOR61</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR62</name>
			<displayName>IPRIOR62</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xBE0</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR62</name>
					<description>IPRIOR62</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
		<register>
			<name>R32_PFIC_IPRIOR63</name>
			<displayName>IPRIOR63</displayName>
			<description>Interrupt Priority configuration Register</description>
			<addressOffset>0xC00</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>IPRIOR63</name>
					<description>IPRIOR63</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>	
				
		<register>
			<name>R32_PFIC_SCTLR</name>
			<displayName>SCTLR</displayName>
			<description>System Control Register</description>
			<addressOffset>0xD10</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>SLEEPONEXIT</name>
					<description>SLEEPONEXIT</description>
					<bitOffset>1</bitOffset>
					<bitWidth>1</bitWidth>
				</field>
				<field>
					<name>SLEEPDEEP</name>
					<description>SLEEPDEEP</description>
					<bitOffset>2</bitOffset>
					<bitWidth>1</bitWidth>
				</field>
				<field>
				<name>WFITOWFE</name>
					<description>WFITOWFE</description>
					<bitOffset>3</bitOffset>
					<bitWidth>1</bitWidth>
				</field>
		  		<field>
					<name>SEVONPEND</name>
					<description>SEVONPEND</description>
					<bitOffset>4</bitOffset>
					<bitWidth>1</bitWidth>
				</field>
				<field>
					<name>SETEVENT</name>
					<description>SETEVENT</description>
					<bitOffset>5</bitOffset>
					<bitWidth>1</bitWidth>
				</field>
		 	</fields>
		</register>       
	  </registers>
	</peripheral>


	<peripheral>
		<name>Systick</name>
		<description>Systick register</description>
		<groupName>Systick</groupName>
		<baseAddress>0xE000F000</baseAddress>
		<addressBlock>
			<offset>0x0</offset>
			<size>0x100</size>					
			<usage>registers</usage>
	  	</addressBlock>
		 <registers>
			<register>
				<name>R32_STK_CTLR</name>
				<displayName>STK_CTLR</displayName>
				<description>Systick counter control register</description>
				<addressOffset>0x00</addressOffset>
				<size>0x20</size>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>STE</name>
						<description>Systick counter enable</description>
						<access>read-write</access>
						<bitOffset>0</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>STIE</name>
						<description>Systick counter interrupt enable</description>
						<access>read-write</access>
						<bitOffset>1</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>STCLK</name>
						<description>System counter clock Source selection</description>
						<access>read-write</access>
						<bitOffset>2</bitOffset>
						<bitWidth>1</bitWidth>
					</field>
					<field>
						<name>STRELOAD</name>
						<description>System counter reload control</description>
						<access>read-write</access>
						<bitOffset>8</bitOffset>
						<bitWidth>1</bitWidth>
					</field>					
		 		</fields>
		</register> 
		<register>
			<name>R32_STK_CNTL</name>
			<description>Systick counter low register</description>
			<addressOffset>0x04</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>CNTL</name>
						<description>CNTL</description>
						<bitOffset>0</bitOffset>
						<bitWidth>32</bitWidth>
					</field>
				</fields>
		</register>   
		<register>
			<name>R32_STK_CNTH</name>
			<description>Systick counter high register</description>
			<addressOffset>0x08</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>CNTH</name>
					<description>CNTH</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register> 
		<register>
			<name>R32_STK_CMPLR</name>
			<description>Systick compare low register</description>
			<addressOffset>0x0C</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>CMPL</name>
					<description>CMPL</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
			</fields>
		</register>    
		<register>
			<name>R32_STK_CMPHR</name>
			<description>Systick compare high register</description>
			<addressOffset>0x10</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>CMPH</name>
					<description>CMPH</description>
					<bitOffset>0</bitOffset>
					<bitWidth>32</bitWidth>
				</field>
		  	</fields>
		</register>        
		<register>
			<name>R32_STK_CNTFG</name>
			<description>Systick counter flag</description>
			<addressOffset>0x14</addressOffset>
			<size>0x20</size>
			<access>read-write</access>
			<resetValue>0x00000000</resetValue>
			<fields>
				<field>
					<name>SWIE</name>
					<description>System soft interrupt enable</description>
					<bitOffset>0</bitOffset>
					<bitWidth>1</bitWidth>
				</field>
				<field>
					<name>CNTIF</name>
					<description>Systick counter clear zero flag</description>
					<bitOffset>1</bitOffset>
					<bitWidth>1</bitWidth>
				</field>					
		  	</fields>
		</register>  
	  </registers>
	</peripheral>

	<peripheral>
		<name>EMMC</name>
		<description>EMMC register</description>
		<groupName>EMMC</groupName>
		<baseAddress>0x4000A000</baseAddress>
		<addressBlock>
			<offset>0x00</offset>
			<size>0x400</size>
			<usage>registers</usage>
		</addressBlock>		
 		<registers>
			<register>
				<name>R16_EMMC_CLK_DIV</name>
				<description>SD clock divider register</description>
				<addressOffset>0x38</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0213</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_DIV_MASK</name>
						<description>clk div</description>
						<bitRange>[4:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_CLKOE</name>
						<description>chip output sdclk oe</description>
						<bitRange>[8:8]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_CLKMode</name>
						<description>EMMC clock frequency mode selection bit</description>
						<bitRange>[9:9]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_PHASEINV</name>
						<description>invert chip output sdclk phase</description>
						<bitRange>[10:10]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_EMMC_ARGUMENT</name>
				<description>SD 32bits command argument register</description>
				<addressOffset>0x00</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
				    <field>
						<name>EMMC_ARGUMENT</name>
						<description>32 bit command parameter register</description>
						<bitRange>[31:0]</bitRange>
					</field>
				</fields>	
			</register>
			<register>
				<name>R16_EMMC_CMD_SET</name>
				<description>SD 16bits cmd setting register</description>
				<addressOffset>0x04</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_CMDIDX_MASK</name>
						<description>the index number of the currently sent command</description>
						<bitRange>[5:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_RPTY_MASK</name>
						<description>current respone type</description>
						<bitRange>[9:8]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_CKCRC</name>
						<description>check the response CRC</description>
						<bitRange>[10:10]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_CKIDX</name>
						<description>check the response command index</description>
						<bitRange>[11:11]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_EMMC_RESPONSE0</name>
				<description>SD 128bits response register, [31:0] 32bits </description>
				<addressOffset>0x08</addressOffset>
				<size>32</size>
				<access>read-only</access>
				<resetValue>0x00000000</resetValue>
				<fields>
				    <field>
						<name>R32_EMMC_RESPONSE0</name>
						<description>response parameter register</description>
						<bitRange>[31:0]</bitRange>
					</field>
                </fields>
			</register>
			<register>
				<name>R32_EMMC_RESPONSE1</name>
				<description>SD 128bits response register, [63:32] 32bits </description>
				<addressOffset>0x0C</addressOffset>
				<size>32</size>
				<access>read-only</access>
				<fields>
					<field>
						<name>R32_EMMC_RESPONSE1</name>
						<description>response parameter register</description>
						<bitRange>[63:32]</bitRange>
					</field>
				</fields>	
			</register>
			<register>
				<name>R32_EMMC_RESPONSE2</name>
				<description>SD 128bits response register, [95:64] 32bits </description>
				<addressOffset>0x10</addressOffset>
				<size>32</size>
				<access>read-only</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_EMMC_RESPONSE2</name>
						<description>response parameter register</description>
						<bitRange>[95:64]</bitRange>
					</field>
				</fields>	
			</register>
            <register>
				<name>R32_EMMC_RESPONSE3</name>
				<description>SD 128bits response register, [127:96] 32bits </description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>read-only</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_EMMC_RESPONSE3</name>
						<description>response parameter register</description>
						<bitRange>[127:96]</bitRange>
					</field>
				</fields>	
			</register>
			<register>
				<name>R32_EMMC_WRITE_CONT</name>
				<description>Multiplexing register of the EMMC_RESPONSE3,[127:96] 32bits</description>
				<addressOffset>0x14</addressOffset>
				<size>32</size>
				<access>write-only</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>R32_EMMC_WRITE_CONT</name>
						<description>response parameter register</description>
						<bitRange>[127:96]</bitRange>
					</field>
				</fields>
			</register>
 			<register>
				<name>R8_EMMC_CONTROL</name>
				<description>SD 8bits control register</description>
				<addressOffset>0x18</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x15</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_LW_MASK</name>
						<description>effctive data width for sending or receiving data </description>
						<bitRange>[1:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_ALL_CLR</name>
						<description>reset all the inner logic, default is valid</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_DMAEN</name>
						<description>enable the dma </description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_RST_LGC</name>
						<description>reset the data tran/recv logic</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_NEGSMP</name>
						<description>controller use nagedge sample cmd</description>
						<bitRange>[5:5]</bitRange>
					</field>
				</fields>
			</register>
 			<register>
				<name>R8_EMMC_TIMEOUT</name>
				<description>SD 8bits data timeout value</description>
				<addressOffset>0x1C</addressOffset>
				<size>8</size>
				<access>read-write</access>
				<resetValue>0x0C</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_TOCNT_MASK</name>
						<description>response /data timeout configuration  </description>
						<bitRange>[3:0]</bitRange>
					</field>
				</fields>
			</register>
            <register>
				<name>R32_EMMC_STATUS</name>
				<description>SD status</description>
				<addressOffset>0x20</addressOffset>
				<size>32</size>
				<access>read-only</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>MASK_BLOCK_NUM</name>
						<description>the number of blocks successfully transmitted in the current multi-block transmission </description>
						<bitRange>[15:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_CMDSTA</name>
						<description>indicate cmd line is high level now </description>
						<bitRange>[16:16]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_DAT0STA</name>
						<description>indicate dat[0] line is high level now</description>
						<bitRange>[17:17]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R16_EMMC_INT_FG</name>
				<description>SD 16bits interrupt flag register</description>
				<addressOffset>0x24</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_IF_RE_TMOUT</name>
						<description>indicate when expect the response, timeout </description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IF_RECRC_WR</name>
						<description>indicate CRC error of the response </description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IF_REIDX_ER</name>
						<description>indicate INDEX error of the response </description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IF_CMDDONE</name>
						<description>when cmd hasn't response, indicate cmd has been sent, when cmd has a response, indicate cmd has bee sent and has received the response</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IF_DATTMO</name>
						<description>data line busy timeout </description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IF_TRANERR</name>
						<description>last block have encountered a CRC error </description>
						<bitRange>[5:5]</bitRange>
					</field>
                    <field>
						<name>RB_EMMC_IF_TRANDONE</name>
						<description>all the blocks have been tran/recv successfully </description>
						<bitRange>[6:6]</bitRange>
					</field>
                    <field>
						<name>RB_EMMC_IF_BKGAP</name>
						<description>every block gap interrupt when multiple read or write, allow drive change the DMA address at this moment  </description>
						<bitRange>[7:7]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IF_FIFO_OV</name>
						<description>fifo overflow, when write sd, indicate empty overflow, when read sd, indicate full overflow</description>
						<bitRange>[8:8]</bitRange>
					</field>
					 <field>
						<name>RB_EMMC_IF_SDIOINT</name>
						<description>interrupt from SDIO card inside </description>
						<bitRange>[9:9]</bitRange>
					</field>
				</fields>				
			</register>
			<register>
				<name>R16_EMMC_INT_EN</name>
				<description>SD 16bits interrupt enable register</description>
				<addressOffset>0x28</addressOffset>
				<size>16</size>
				<access>read-write</access>
				<resetValue>0x0000</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_IE_RE_TMOUT</name>
						<description>command response timeout interrupt enable</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_RECRC_WR</name>
						<description>response CRC check error interrupt  enable </description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_REIDX_ER</name>
						<description>response index check error interrupt  enable</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_CMDDONE</name>
						<description>command completion interrupt enable</description>
						<bitRange>[3:3]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_DATTMO</name>
						<description>data timeout interrupt enable</description>
						<bitRange>[4:4]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_TRANERR</name>
						<description>blocks transfer CRC error interrupt enable</description>
						<bitRange>[5:5]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_TRANDONE</name>
						<description>all blocks transfer complete interrupt enable</description>
						<bitRange>[6:6]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_BKGAP</name>
						<description>single block transmission completion interrupt enable</description>
						<bitRange>[7:7]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_FIFO_OV</name>
						<description>FIFO overflow interrupt enable</description>
						<bitRange>[8:8]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_IE_SDIOINT</name>
						<description>SDIO card interrupt enable</description>
						<bitRange>[9:9]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_EMMC_DMA_BEG1</name>
				<description>SD 16bits DMA start address register when to operate</description>
				<addressOffset>0x2C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_DMAAD1_MASK</name>
						<description>start address of read-write data buffer,the lower 4 bits are fixed to 0</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_EMMC_BLOCK_CFG</name>
				<description>SD 32bits data counter, [15:0] number of blocks this time will tran/recv, [27:16] block sise(byte number) of every block in this time tran/recv</description>
				<addressOffset>0x30</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_BKNUM_MASK</name>
						<description>the number of blocks to be transferred</description>
						<bitRange>[15:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_BKSIZE_MASK</name>
						<description>single block transfer size</description>
						<bitRange>[27:16]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_EMMC_TRAN_MODE</name>
				<description>SD TRANSFER MODE register</description>
				<addressOffset>0x34</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_DMA_DIR</name>
						<description>set DMA direction is controller to emmc card</description>
						<bitRange>[0:0]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_GAP_STOP</name>
						<description>clock stop mode after block completion</description>
						<bitRange>[1:1]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_MODE_BOOT</name>
						<description>enable emmc boot mode</description>
						<bitRange>[2:2]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_AUTOGAPSTOP</name>
						<description>enable auto set bTM_GAP_STOP when tran start</description>
						<bitRange>[4:4]</bitRange>
					</field>
				    <field>
						<name>RB_EMMC_FIFO_RDY</name>
						<description>FIFO ready select signal when writing EMMC</description>
						<bitRange>[7:6]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_DMATN_CNT</name>
						<description>in double buffer mode,set the block count value of buffer switch</description>
						<bitRange>[14:8]</bitRange>
					</field>
					<field>
						<name>RB_EMMC_DULEDMA_EN</name>
						<description>enable double buffer dma</description>
						<bitRange>[16:16]</bitRange>
					</field>
				</fields>
			</register>
			<register>
				<name>R32_EMMC_DMA_BEG2</name>
				<description>SD 16bits DMA start address register when to operate</description>
				<addressOffset>0x3C</addressOffset>
				<size>32</size>
				<access>read-write</access>
				<resetValue>0x00000000</resetValue>
				<fields>
					<field>
						<name>RB_EMMC_DMAAD2_MASK</name>
						<description>block DMA start address register</description>
						<bitRange>[16:0]</bitRange>
					</field>
				</fields>
			</register>
		</registers>
    </peripheral>
 </peripherals>
</device>