Update to edition 2018 (#29)

* edition 2018

* revert incremeentaal

* ed2018 examples

Cargo.toml

@@ -7,6 +7,7 @@ license = "MIT OR Apache-2.0"
 name = "stm32f1xx-hal"
 repository = "https://github.com/stm32-rs/stm32f1xx-hal"
 documentation = "https://docs.rs/stm32f1xx-hal"
+edition = "2018"
 version = "0.2.0"
 
 [package.metadata.docs.rs]
@@ -31,6 +32,7 @@ features = ["unproven"]
 version = "0.2.2"
 
 [dev-dependencies]
+panic-halt = "0.2.0"
 panic-semihosting = "0.5.1"
 panic-itm = "0.4.0"
 # cortex-m-rtfm = "0.3.1"

examples/blinky.rs

@@ -5,22 +5,21 @@
 #![no_std]
 #![no_main]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
-#[macro_use(block)]
-extern crate nb;
-
-use hal::prelude::*;
-use hal::stm32;
-use hal::timer::Timer;
-use rt::{entry, exception, ExceptionFrame};
+extern crate panic_halt;
+
+use nb::block;
+
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    timer::Timer,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
     let cp = cortex_m::Peripherals::take().unwrap();
-    let dp = stm32::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
     let mut rcc = dp.RCC.constrain();
@@ -44,13 +43,3 @@ fn main() -> ! {
         led.set_low();
     }
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/blinky_rtc.rs

@@ -5,21 +5,20 @@
 #![no_std]
 #![no_main]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
-#[macro_use(block)]
-extern crate nb;
-
-use hal::prelude::*;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
-use hal::rtc::Rtc;
+extern crate panic_halt;
+
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    rtc::Rtc,
+};
+
+use nb::block;
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let dp = stm32::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
 
     let mut pwr = dp.PWR;
     let mut rcc = dp.RCC.constrain();
@@ -51,13 +50,3 @@ fn main() -> ! {
         }
     }
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/delay.rs

@@ -5,19 +5,18 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
+extern crate panic_halt;
 
-use hal::delay::Delay;
-use hal::prelude::*;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    delay::Delay,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let dp = stm32::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
@@ -42,13 +41,3 @@ fn main() -> ! {
         delay.delay_ms(1_000_u16);
     }
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/hello.rs

@@ -5,17 +5,15 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m_rt as rt;
-extern crate cortex_m_semihosting as sh;
 extern crate panic_semihosting;
+
 extern crate stm32f1xx_hal;
+use cortex_m_semihosting::hprintln;
 
-use core::fmt::Write;
-use rt::entry;
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let mut hstdout = sh::hio::hstdout().unwrap();
-    writeln!(hstdout, "Hello, world!").unwrap();
+    hprintln!("Hello, world!").unwrap();
     loop {}
 }

examples/itm.rs

@@ -3,13 +3,11 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m_rt as rt;
-#[macro_use]
-extern crate cortex_m;
 extern crate panic_itm;
+use cortex_m::iprintln;
 extern crate stm32f1xx_hal;
 
-use rt::{entry, exception, ExceptionFrame};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
@@ -20,13 +18,3 @@ fn main() -> ! {
 
     loop {}
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/led.rs

@@ -5,17 +5,18 @@
 #![no_main]
 #![no_std]
 
+extern crate panic_halt;
 extern crate cortex_m_rt as rt;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
 
-use hal::prelude::*;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let p = stm32::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
     let mut gpioc = p.GPIOC.split(&mut rcc.apb2);
@@ -28,13 +29,3 @@ fn main() -> ! {
 
     loop {}
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/mfrc522.rs

@@ -3,23 +3,22 @@
 #![no_main]
 #![no_std]
 
-#[macro_use]
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate mfrc522;
 extern crate panic_itm;
-extern crate stm32f1xx_hal as hal;
 
-use hal::prelude::*;
-use hal::spi::Spi;
-use hal::stm32;
+use cortex_m::iprintln;
+
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    spi::Spi,
+};
 use mfrc522::Mfrc522;
-use rt::{entry, exception, ExceptionFrame};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
     let mut cp = cortex_m::Peripherals::take().unwrap();
-    let dp = stm32::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
 
     let _stim = &mut cp.ITM.stim[0];
     let mut rcc = dp.RCC.constrain();
@@ -57,13 +56,3 @@ fn main() -> ! {
         }
     }
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/nojtag.rs

@@ -5,17 +5,17 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m_rt as rt;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
+extern crate panic_halt;
 
-use hal::prelude::*;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let p = stm32::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut rcc = p.RCC.constrain();
     let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
@@ -27,13 +27,3 @@ fn main() -> ! {
 
     loop {}
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/panics.rs

@@ -0,0 +1,29 @@
+//! Prints "Hello, world" on the OpenOCD console
+
+#![deny(unsafe_code)]
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+extern crate panic_semihosting;
+//extern crate panic_itm;
+extern crate stm32f1xx_hal;
+use cortex_m_semihosting::hprintln;
+
+use cortex_m_rt::{entry, exception, ExceptionFrame};
+
+#[entry]
+fn main() -> ! {
+    hprintln!("Hello, world!").unwrap();
+    loop {}
+}
+
+#[exception]
+fn HardFault(ef: &ExceptionFrame) -> ! {
+    panic!("{:#?}", ef);
+}
+
+#[exception]
+fn DefaultHandler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}

examples/pwm.rs

@@ -5,19 +5,18 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
+extern crate panic_halt;
 
 use cortex_m::asm;
-use hal::prelude::*;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let p = stm32::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
     let mut rcc = p.RCC.constrain();
@@ -79,13 +78,3 @@ fn main() -> ! {
 
     loop {}
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/qei.rs

@@ -5,24 +5,21 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate cortex_m_semihosting as semihosting;
 extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
 
-use core::fmt::Write;
+use cortex_m_semihosting::hprintln;
 
-use hal::delay::Delay;
-use hal::prelude::*;
-use hal::qei::Qei;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
-use semihosting::hio;
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    delay::Delay,
+    qei::Qei,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let dp = stm32::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
@@ -50,7 +47,6 @@ fn main() -> ! {
     let qei = Qei::tim4(dp.TIM4, (c1, c2), &mut afio.mapr, &mut rcc.apb1);
     let mut delay = Delay::new(cp.SYST, clocks);
 
-    let mut hstdout = hio::hstdout().unwrap();
     loop {
         let before = qei.count();
         delay.delay_ms(1_000_u16);
@@ -58,16 +54,6 @@ fn main() -> ! {
 
         let elapsed = after.wrapping_sub(before) as i16;
 
-        writeln!(hstdout, "{}", elapsed).unwrap();
+        hprintln!("{}", elapsed).unwrap();
     }
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/rtc.rs

@@ -5,26 +5,20 @@
 #![no_std]
 #![no_main]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-extern crate cortex_m_semihosting as sh;
 extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
 
-use hal::prelude::*;
-use rt::{entry, exception, ExceptionFrame};
+use cortex_m_semihosting::hprintln;
 
-use sh::hio;
-
-use core::fmt::Write;
-
-use hal::rtc::Rtc;
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    rtc::Rtc,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let mut hstdout = hio::hstdout().unwrap();
-
-    let p = hal::stm32::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut pwr = p.PWR;
     let mut rcc = p.RCC.constrain();
@@ -33,16 +27,6 @@ fn main() -> ! {
     let rtc = Rtc::rtc(p.RTC, &mut backup_domain);
 
     loop {
-        writeln!(hstdout, "time: {}", rtc.seconds()).unwrap();
+        hprintln!("time: {}", rtc.seconds()).unwrap();
     }
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

examples/serial.rs

@@ -7,22 +7,22 @@
 #![no_main]
 #![no_std]
 
-extern crate cortex_m;
-extern crate cortex_m_rt as rt;
-#[macro_use(block)]
-extern crate nb;
-extern crate panic_semihosting;
-extern crate stm32f1xx_hal as hal;
+extern crate panic_halt;
 
 use cortex_m::asm;
-use hal::prelude::*;
-use hal::serial::Serial;
-use hal::stm32;
-use rt::{entry, exception, ExceptionFrame};
+
+use nb::block;
+
+use stm32f1xx_hal::{
+    prelude::*,
+    pac,
+    serial::Serial,
+};
+use cortex_m_rt::entry;
 
 #[entry]
 fn main() -> ! {
-    let p = stm32::Peripherals::take().unwrap();
+    let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
     let mut rcc = p.RCC.constrain();
@@ -73,13 +73,3 @@ fn main() -> ! {
 
     loop {}
 }
-
-#[exception]
-fn HardFault(ef: &ExceptionFrame) -> ! {
-    panic!("{:#?}", ef);
-}
-
-#[exception]
-fn DefaultHandler(irqn: i16) {
-    panic!("Unhandled exception (IRQn = {})", irqn);
-}

src/afio.rs

@@ -1,7 +1,7 @@
 //! # Alternate Function I/Os
-use stm32::{afio, AFIO};
+use crate::pac::{afio, AFIO};
 
-use rcc::APB2;
+use crate::rcc::APB2;
 
 pub trait AfioExt {
     fn constrain(self, apb2: &mut APB2) -> Parts;

src/backup_domain.rs

@@ -13,7 +13,7 @@
   Only the RTC functionality is currently implemented.
 */
 
-use stm32::BKP;
+use crate::pac::BKP;
 
 /**
   The existence of this struct indicates that writing to the the backup

src/delay.rs

@@ -4,8 +4,8 @@ use cast::u32;
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
 
-use hal::blocking::delay::{DelayMs, DelayUs};
-use rcc::Clocks;
+use crate::hal::blocking::delay::{DelayMs, DelayUs};
+use crate::rcc::Clocks;
 
 /// System timer (SysTick) as a delay provider
 pub struct Delay {

src/dma.rs

@@ -4,7 +4,7 @@
 use core::marker::PhantomData;
 use core::ops;
 
-use rcc::AHB;
+use crate::rcc::AHB;
 
 #[derive(Debug)]
 pub enum Error {
@@ -130,7 +130,7 @@ macro_rules! dma {
             pub mod $dmaX {
                 use core::sync::atomic::{self, Ordering};
 
-                use stm32::{$DMAX, dma1};
+                use crate::pac::{$DMAX, dma1};
 
                 use dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W};
                 use rcc::AHB;

src/flash.rs

@@ -1,6 +1,6 @@
 //! Flash memory
 
-use stm32::{flash, FLASH};
+use crate::pac::{flash, FLASH};
 
 /// Extension trait to constrain the FLASH peripheral
 pub trait FlashExt {

src/gpio.rs

@@ -5,7 +5,7 @@
 
 use core::marker::PhantomData;
 
-use rcc::APB2;
+use crate::rcc::APB2;
 
 /// Extension trait to split a GPIO peripheral in independent pins and registers
 pub trait GpioExt {
@@ -59,10 +59,10 @@ macro_rules! gpio {
         pub mod $gpiox {
             use core::marker::PhantomData;
 
-            use hal::digital::{InputPin, OutputPin, StatefulOutputPin, toggleable};
-            use stm32::{$gpioy, $GPIOX};
+            use crate::hal::digital::{InputPin, OutputPin, StatefulOutputPin, toggleable};
+            use crate::pac::{$gpioy, $GPIOX};
 
-            use rcc::APB2;
+            use crate::rcc::APB2;
             use super::{
                 Alternate, Floating, GpioExt, Input,
                 OpenDrain,

src/i2c.rs

@@ -1,14 +1,13 @@
 //! Inter-Integrated Circuit (I2C) bus
 
-use afio::MAPR;
-use gpio::gpiob::{PB10, PB11, PB6, PB7, PB8, PB9};
-use gpio::{Alternate, OpenDrain};
-use hal::blocking::i2c::{Read, Write, WriteRead};
+use crate::afio::MAPR;
+use crate::gpio::gpiob::{PB10, PB11, PB6, PB7, PB8, PB9};
+use crate::gpio::{Alternate, OpenDrain};
+use crate::hal::blocking::i2c::{Read, Write, WriteRead};
 use nb::Error::{Other, WouldBlock};
 use nb::{Error as NbError, Result as NbResult};
-use rcc::{Clocks, APB1};
-use stm32::DWT;
-use stm32::{I2C1, I2C2};
+use crate::rcc::{Clocks, APB1};
+use crate::pac::{DWT, I2C1, I2C2};
 
 /// I2C error
 #[derive(Debug, Eq, PartialEq)]

src/lib.rs

@@ -37,19 +37,16 @@
 
 #![no_std]
 
-extern crate cast;
-extern crate cortex_m;
-extern crate embedded_hal as hal;
-extern crate nb;
-extern crate void;
-
-pub extern crate stm32f1;
+use embedded_hal as hal;
 
 #[cfg(feature = "stm32f100")]
-pub use stm32f1::stm32f100 as stm32;
+pub use stm32f1::stm32f100 as pac;
 
 #[cfg(feature = "stm32f103")]
-pub use stm32f1::stm32f103 as stm32;
+pub use stm32f1::stm32f103 as pac;
+
+pub use crate::pac as device;
+pub use crate::pac as stm32;
 
 pub mod afio;
 pub mod bb;

src/prelude.rs

@@ -1,14 +1,14 @@
-pub use afio::AfioExt as _stm32_hal_afio_AfioExt;
-pub use dma::DmaChannel as _stm32_hal_dma_DmaChannel;
-pub use dma::DmaExt as _stm32_hal_dma_DmaExt;
-pub use flash::FlashExt as _stm32_hal_flash_FlashExt;
-pub use gpio::GpioExt as _stm32_hal_gpio_GpioExt;
-pub use hal::digital::StatefulOutputPin as _embedded_hal_digital_StatefulOutputPin;
-pub use hal::digital::ToggleableOutputPin as _embedded_hal_digital_ToggleableOutputPin;
-pub use hal::prelude::*;
+pub use crate::afio::AfioExt as _stm32_hal_afio_AfioExt;
+pub use crate::dma::DmaChannel as _stm32_hal_dma_DmaChannel;
+pub use crate::dma::DmaExt as _stm32_hal_dma_DmaExt;
+pub use crate::flash::FlashExt as _stm32_hal_flash_FlashExt;
+pub use crate::gpio::GpioExt as _stm32_hal_gpio_GpioExt;
+pub use crate::hal::digital::StatefulOutputPin as _embedded_hal_digital_StatefulOutputPin;
+pub use crate::hal::digital::ToggleableOutputPin as _embedded_hal_digital_ToggleableOutputPin;
+pub use crate::hal::prelude::*;
 #[cfg(not(feature = "stm32f100"))]
-pub use pwm::PwmExt as _stm32_hal_pwm_PwmExt;
-pub use rcc::RccExt as _stm32_hal_rcc_RccExt;
-//pub use serial::ReadDma as _stm32_hal_serial_ReadDma;
-//pub use serial::WriteDma as _stm32_hal_serial_WriteDma;
-pub use time::U32Ext as _stm32_hal_time_U32Ext;
+pub use crate::pwm::PwmExt as _stm32_hal_pwm_PwmExt;
+pub use crate::rcc::RccExt as _stm32_hal_rcc_RccExt;
+//pub use crate::serial::ReadDma as _stm32_hal_serial_ReadDma;
+//pub use crate::serial::WriteDma as _stm32_hal_serial_WriteDma;
+pub use crate::time::U32Ext as _stm32_hal_time_U32Ext;

src/pwm.rs

@@ -4,16 +4,16 @@ use core::marker::PhantomData;
 use core::mem;
 
 use cast::{u16, u32};
-use hal;
-use stm32::{TIM2, TIM3, TIM4};
+use crate::hal;
+use crate::pac::{TIM2, TIM3, TIM4};
 
-use afio::MAPR;
-use bb;
-use gpio::gpioa::{PA0, PA1, PA2, PA3, PA6, PA7};
-use gpio::gpiob::{PB0, PB1, PB6, PB7, PB8, PB9};
-use gpio::{Alternate, PushPull};
-use rcc::{Clocks, APB1};
-use time::Hertz;
+use crate::afio::MAPR;
+use crate::bb;
+use crate::gpio::gpioa::{PA0, PA1, PA2, PA3, PA6, PA7};
+use crate::gpio::gpiob::{PB0, PB1, PB6, PB7, PB8, PB9};
+use crate::gpio::{Alternate, PushPull};
+use crate::rcc::{Clocks, APB1};
+use crate::time::Hertz;
 
 pub trait Pins<TIM> {
     const REMAP: u8;
@@ -93,7 +93,7 @@ impl Pins<TIM4>
 pub trait PwmExt: Sized {
     fn pwm<PINS, T>(
         self,
-        PINS,
+        _: PINS,
         mapr: &mut MAPR,
         frequency: T,
         clocks: Clocks,

src/qei.rs

@@ -1,14 +1,14 @@
 //! # Quadrature Encoder Interface
 use core::u16;
 
-use hal::{self, Direction};
-use stm32::{TIM2, TIM3, TIM4};
-
-use afio::MAPR;
-use gpio::gpioa::{PA0, PA1, PA6, PA7};
-use gpio::gpiob::{PB6, PB7};
-use gpio::{Floating, Input};
-use rcc::APB1;
+use crate::hal::{self, Direction};
+use crate::pac::{TIM2, TIM3, TIM4};
+
+use crate::afio::MAPR;
+use crate::gpio::gpioa::{PA0, PA1, PA6, PA7};
+use crate::gpio::gpiob::{PB6, PB7};
+use crate::gpio::{Floating, Input};
+use crate::rcc::APB1;
 
 pub trait Pins<TIM> {
     const REMAP: u8;

src/rcc.rs

@@ -3,12 +3,12 @@
 use core::cmp;
 
 use cast::u32;
-use stm32::{self, rcc, RCC, PWR};
+use crate::pac::{rcc, RCC, PWR};
 
-use flash::ACR;
-use time::Hertz;
+use crate::flash::ACR;
+use crate::time::Hertz;
 
-use backup_domain::BackupDomain;
+use crate::backup_domain::BackupDomain;
 
 
 /// Extension trait that constrains the `RCC` peripheral
@@ -333,7 +333,7 @@ pub struct BKP {
 
 impl BKP {
     /// Enables write access to the registers in the backup domain
-    pub fn constrain(self, bkp: stm32::BKP, apb1: &mut APB1, pwr: &mut PWR) -> BackupDomain {
+    pub fn constrain(self, bkp: crate::pac::BKP, apb1: &mut APB1, pwr: &mut PWR) -> BackupDomain {
         // Enable the backup interface by setting PWREN and BKPEN
         apb1.enr().modify(|_r, w| {
             w

src/rtc.rs

@@ -12,7 +12,7 @@
   See examples/rtc.rs and examples/blinky_rtc.rs for usage examples.
 */
 
-use stm32::{RTC, RCC};
+use crate::pac::{RTC, RCC};
 
 use crate::backup_domain::BackupDomain;
 

src/serial.rs

@@ -6,7 +6,7 @@
 //! ## Example usage:
 //!  ```rust
 //! // prelude: create handles to the peripherals and registers
-//! let p = stm32::Peripherals::take().unwrap();
+//! let p = crate::pac::Peripherals::take().unwrap();
 //! let cp = cortex_m::Peripherals::take().unwrap();
 //! let mut flash = p.FLASH.constrain();
 //! let mut rcc = p.RCC.constrain();
@@ -41,19 +41,19 @@ use core::ptr;
 use core::sync::atomic::{self, Ordering};
 
 use cast::u16;
-use hal;
+use crate::hal;
 use nb;
-use stm32::{USART1, USART2, USART3};
+use crate::pac::{USART1, USART2, USART3};
 use void::Void;
 
-use afio::MAPR;
-//use dma::{dma1, CircBuffer, Static, Transfer, R, W};
-use dma::{CircBuffer, Static, Transfer, R, W};
-use gpio::gpioa::{PA10, PA2, PA3, PA9};
-use gpio::gpiob::{PB10, PB11, PB6, PB7};
-use gpio::{Alternate, Floating, Input, PushPull};
-use rcc::{Clocks, APB1, APB2};
-use time::Bps;
+use crate::afio::MAPR;
+//use crate::dma::{dma1, CircBuffer, Static, Transfer, R, W};
+use crate::dma::{CircBuffer, Static, Transfer, R, W};
+use crate::gpio::gpioa::{PA10, PA2, PA3, PA9};
+use crate::gpio::gpiob::{PB10, PB11, PB6, PB7};
+use crate::gpio::{Alternate, Floating, Input, PushPull};
+use crate::rcc::{Clocks, APB1, APB2};
+use crate::time::Bps;
 
 /// Interrupt event
 pub enum Event {
@@ -239,7 +239,7 @@ macro_rules! hal {
                 }
             }
 
-            impl hal::serial::Read<u8> for Rx<$USARTX> {
+            impl crate::hal::serial::Read<u8> for Rx<$USARTX> {
                 type Error = Error;
 
                 fn read(&mut self) -> nb::Result<u8, Error> {
@@ -427,7 +427,7 @@ macro_rules! hal {
             }
             */
 
-            impl hal::serial::Write<u8> for Tx<$USARTX> {
+            impl crate::hal::serial::Write<u8> for Tx<$USARTX> {
                 type Error = Void;
 
                 fn flush(&mut self) -> nb::Result<(), Self::Error> {

src/spi.rs

@@ -2,17 +2,17 @@
 
 use core::ptr;
 
-use hal;
-pub use hal::spi::{Mode, Phase, Polarity};
+use crate::hal;
+pub use crate::hal::spi::{Mode, Phase, Polarity};
 use nb;
-use stm32::{SPI1, SPI2};
+use crate::pac::{SPI1, SPI2};
 
-use afio::MAPR;
-use gpio::gpioa::{PA5, PA6, PA7};
-use gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
-use gpio::{Alternate, Floating, Input, PushPull};
-use rcc::{Clocks, APB1, APB2};
-use time::Hertz;
+use crate::afio::MAPR;
+use crate::gpio::gpioa::{PA5, PA6, PA7};
+use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
+use crate::gpio::{Alternate, Floating, Input, PushPull};
+use crate::rcc::{Clocks, APB1, APB2};
+use crate::time::Hertz;
 
 /// SPI error
 #[derive(Debug)]
@@ -174,7 +174,7 @@ macro_rules! hal {
                 }
             }
 
-            impl<PINS> hal::spi::FullDuplex<u8> for Spi<$SPIX, PINS> {
+            impl<PINS> crate::hal::spi::FullDuplex<u8> for Spi<$SPIX, PINS> {
                 type Error = Error;
 
                 fn read(&mut self) -> nb::Result<u8, Error> {
@@ -217,9 +217,9 @@ macro_rules! hal {
 
             }
 
-            impl<PINS> ::hal::blocking::spi::transfer::Default<u8> for Spi<$SPIX, PINS> {}
+            impl<PINS> crate::hal::blocking::spi::transfer::Default<u8> for Spi<$SPIX, PINS> {}
 
-            impl<PINS> ::hal::blocking::spi::write::Default<u8> for Spi<$SPIX, PINS> {}
+            impl<PINS> crate::hal::blocking::spi::write::Default<u8> for Spi<$SPIX, PINS> {}
         )+
     }
 }

src/time.rs

@@ -2,7 +2,7 @@
 
 use cortex_m::peripheral::DWT;
 
-use rcc::Clocks;
+use crate::rcc::Clocks;
 
 /// Bits per second
 #[derive(Clone, Copy)]

src/timer.rs

@@ -3,15 +3,15 @@
 use cast::{u16, u32};
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
-use hal::timer::{CountDown, Periodic};
+use crate::hal::timer::{CountDown, Periodic};
 use nb;
-use stm32::{TIM1, TIM2, TIM3, TIM4};
+use crate::pac::{TIM1, TIM2, TIM3, TIM4};
 use void::Void;
 
 use core::any::TypeId;
 
-use rcc::{Clocks, APB1, APB2};
-use time::Hertz;
+use crate::rcc::{Clocks, APB1, APB2};
+use crate::time::Hertz;
 
 /// Interrupt events
 pub enum Event {