Add DAC, UART4, UART5 clock in RCC for the f103 high density line (#318)

* Add DAC, UART4, UART5 clock in RCC for the f103 high density line

CHANGELOG.md

@@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Support for OpenDrain pin configuration on SPI CLK and MOSI pins
 - LSB/MSB bit format selection for `SPI`
 - Support for CAN peripherals with the `bxcan` crate
+- Add DAC, UART4, UART5 clock in RCC for the f103 high density line
 
 ### Fixed
 - Fix > 2 byte i2c reads

src/rcc.rs

@@ -657,6 +657,9 @@ bus! {
 #[cfg(all(feature = "stm32f103", feature = "high",))]
 bus! {
     ADC3 => (APB2, adc3en, adc3rst),
+    DAC => (APB1, dacen, dacrst),
+    UART4 => (APB1, uart4en, uart4rst),
+    UART5 => (APB1, uart5en, uart5rst),
 }
 bus! {
     ADC1 => (APB2, adc1en, adc1rst),