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@@ -115,75 +115,6 @@ impl Pins<USART3> for (PD8<Alternate<PushPull>>, PD9<Input<Floating>>) {
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const REMAP: u8 = 0b11;
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}
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-/// Internal trait for the serial read / write logic.
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-trait UsartReadWrite: Deref<Target=crate::stm32::usart1::RegisterBlock> {
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- fn read(&self) -> nb::Result<u8, Error> {
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- let sr = self.sr.read();
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-
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- // Check for any errors
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- let err = if sr.pe().bit_is_set() {
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- Some(Error::Parity)
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- } else if sr.fe().bit_is_set() {
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- Some(Error::Framing)
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- } else if sr.ne().bit_is_set() {
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- Some(Error::Noise)
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- } else if sr.ore().bit_is_set() {
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- Some(Error::Overrun)
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- } else {
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- None
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- };
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-
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- if let Some(err) = err {
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- // Some error occured. In order to clear that error flag, you have to
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- // do a read from the sr register followed by a read from the dr
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- // register
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- // NOTE(read_volatile) see `write_volatile` below
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- unsafe {
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- ptr::read_volatile(&self.sr as *const _ as *const _);
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- ptr::read_volatile(&self.dr as *const _ as *const _);
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- }
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- Err(nb::Error::Other(err))
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- } else {
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- // Check if a byte is available
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- if sr.rxne().bit_is_set() {
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- // Read the received byte
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- // NOTE(read_volatile) see `write_volatile` below
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- Ok(unsafe {
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- ptr::read_volatile(&self.dr as *const _ as *const _)
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- })
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- } else {
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- Err(nb::Error::WouldBlock)
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- }
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- }
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- }
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-
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- fn write(&self, byte: u8) -> nb::Result<(), Infallible> {
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- let sr = self.sr.read();
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-
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- if sr.txe().bit_is_set() {
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- // NOTE(unsafe) atomic write to stateless register
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- // NOTE(write_volatile) 8-bit write that's not possible through the svd2rust API
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- unsafe {
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- ptr::write_volatile(&self.dr as *const _ as *mut _, byte)
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- }
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- Ok(())
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- } else {
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- Err(nb::Error::WouldBlock)
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- }
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- }
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-
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- fn flush(&self) -> nb::Result<(), Infallible> {
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- let sr = self.sr.read();
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-
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- if sr.tc().bit_is_set() {
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- Ok(())
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- } else {
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- Err(nb::Error::WouldBlock)
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- }
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- }
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-}
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-impl UsartReadWrite for &crate::stm32::usart1::RegisterBlock {}
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-
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pub enum Parity {
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ParityNone,
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ParityEven,
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@@ -261,6 +192,75 @@ pub struct Tx<USART> {
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_usart: PhantomData<USART>,
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}
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+/// Internal trait for the serial read / write logic.
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+trait UsartReadWrite: Deref<Target=crate::stm32::usart1::RegisterBlock> {
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+ fn read(&self) -> nb::Result<u8, Error> {
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+ let sr = self.sr.read();
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+
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+ // Check for any errors
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+ let err = if sr.pe().bit_is_set() {
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+ Some(Error::Parity)
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+ } else if sr.fe().bit_is_set() {
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+ Some(Error::Framing)
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+ } else if sr.ne().bit_is_set() {
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+ Some(Error::Noise)
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+ } else if sr.ore().bit_is_set() {
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+ Some(Error::Overrun)
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+ } else {
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+ None
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+ };
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+
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+ if let Some(err) = err {
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+ // Some error occured. In order to clear that error flag, you have to
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+ // do a read from the sr register followed by a read from the dr
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+ // register
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+ // NOTE(read_volatile) see `write_volatile` below
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+ unsafe {
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+ ptr::read_volatile(&self.sr as *const _ as *const _);
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+ ptr::read_volatile(&self.dr as *const _ as *const _);
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+ }
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+ Err(nb::Error::Other(err))
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+ } else {
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+ // Check if a byte is available
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+ if sr.rxne().bit_is_set() {
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+ // Read the received byte
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+ // NOTE(read_volatile) see `write_volatile` below
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+ Ok(unsafe {
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+ ptr::read_volatile(&self.dr as *const _ as *const _)
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+ })
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+ } else {
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+ Err(nb::Error::WouldBlock)
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+ }
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+ }
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+ }
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+
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+ fn write(&self, byte: u8) -> nb::Result<(), Infallible> {
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+ let sr = self.sr.read();
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+
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+ if sr.txe().bit_is_set() {
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+ // NOTE(unsafe) atomic write to stateless register
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+ // NOTE(write_volatile) 8-bit write that's not possible through the svd2rust API
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+ unsafe {
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+ ptr::write_volatile(&self.dr as *const _ as *mut _, byte)
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+ }
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+ Ok(())
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+ } else {
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+ Err(nb::Error::WouldBlock)
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+ }
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+ }
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+
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+ fn flush(&self) -> nb::Result<(), Infallible> {
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+ let sr = self.sr.read();
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+
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+ if sr.tc().bit_is_set() {
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+ Ok(())
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+ } else {
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+ Err(nb::Error::WouldBlock)
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+ }
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+ }
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+}
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+impl UsartReadWrite for &crate::stm32::usart1::RegisterBlock {}
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+
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macro_rules! hal {
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($(
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$(#[$meta:meta])*
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