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@@ -1,17 +1,6 @@
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/*!
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Real time clock
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-
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- A continuously running clock that counts seconds. It is part of the backup domain which means
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- that the counter is not affected by system resets or standby mode. If Vbat is connected, it is
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- not reset even if the rest of the device is powered off. This allows it to be used to wake the
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- CPU when it is in low power mode.
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-
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- Since it is part of the backup domain, write access to it must be enabled before the RTC can be
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- used. See `backup_domain` for more details.
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-
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- See examples/rtc.rs and examples/blinky_rtc.rs for usage examples.
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*/
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-
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use crate::pac::{RCC, RTC};
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use crate::backup_domain::BackupDomain;
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@@ -23,8 +12,22 @@ use core::convert::Infallible;
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const LSE_HERTZ: u32 = 32_768;
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/**
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- Interface to the real time clock
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+ Real time clock
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+
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+ A continuously running clock that counts seconds¹. It is part of the backup domain which means
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+ that the counter is not affected by system resets or standby mode. If Vbat is connected, it is
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+ not reset even if the rest of the device is powered off. This allows it to be used to wake the
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+ CPU when it is in low power mode.
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+
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+
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+ See [examples/rtc.rs] and [examples/blinky_rtc.rs] for usage examples.
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+
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+ 1: Unless configured to another frequency using [select_frequency](struct.Rtc.html#method.select_frequency)
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+
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+ [examples/rtc.rs]: https://github.com/stm32-rs/stm32f1xx-hal/blob/v0.6.1/examples/rtc.rs
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+ [examples/blinky_rtc.rs]: https://github.com/stm32-rs/stm32f1xx-hal/blob/v0.6.1/examples/blinky_rtc.rs
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*/
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+
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pub struct Rtc {
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regs: RTC,
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}
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@@ -33,6 +36,12 @@ impl Rtc {
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/**
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Initialises the RTC. The `BackupDomain` struct is created by
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`Rcc.bkp.constrain()`.
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+
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+ The frequency is set to 1 Hz.
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+
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+ Since the RTC is part of the backup domain, The RTC counter is not reset by normal resets or
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+ power cycles where (VBAT) still has power. Use [set_time](#method.set_time) if you want to
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+ reset the counter.
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*/
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pub fn rtc(regs: RTC, bkp: &mut BackupDomain) -> Self {
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let mut result = Rtc { regs };
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@@ -123,7 +132,9 @@ impl Rtc {
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self.clear_alarm_flag();
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}
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- /// Enables the RTCALARM interrupt
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+ /// Enables the RTC interrupt to trigger when the counter reaches the alarm value. In addition,
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+ /// if the EXTI controller has been set up correctly, this function also enables the RTCALARM
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+ /// interrupt.
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pub fn listen_alarm(&mut self) {
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// Enable alarm interrupt
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self.perform_write(|s| {
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@@ -131,7 +142,7 @@ impl Rtc {
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})
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}
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- /// Disables the RTCALARM interrupt
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+ /// Stops the RTC alarm from triggering the RTC and RTCALARM interrupts
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pub fn unlisten_alarm(&mut self) {
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// Disable alarm interrupt
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self.perform_write(|s| {
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@@ -147,7 +158,7 @@ impl Rtc {
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self.regs.cnth.read().bits() << 16 | self.regs.cntl.read().bits()
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}
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- /// Enables the RTC second interrupt
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+ /// Enables triggering the RTC interrupt every time the RTC counter is increased
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pub fn listen_seconds(&mut self) {
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self.perform_write(|s| s.regs.crh.modify(|_, w| w.secie().set_bit()))
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}
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