bump stm32f1 0.10.0 (#185)

Co-authored-by: Daniel Egger <daniel@eggers-club.de>

CHANGELOG.md

@@ -7,11 +7,23 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Breaking changes
+
+- Bump `stm32f1` dependency (`0.10.0`)
+- Make traits `rcc::Enable` and `rcc::Reset` public, but `RccBus` sealed
+
+### Added
+
 - Extend the Pwm implementation to cover the full embedded_hal::Pwm API
+- Add `QeiOptions` struct to configure slave mode and auto reload value of QEI interface
+
+### Changed
+
 - Replace default blocking spi Write implementation with an optimized one
 - Use `Deref` for SPI generic implementations instead of macros
-- Make traits `rcc::Enable` and `rcc::Reset` public, but `RccBus` sealed
-- Add `QeiOptions` struct to configure slave mode and auto reload value of QEI interface
+
+### Fixed
+
 - Fix PWM on `TIM1`
 
 ## [v0.5.3] - 2020-01-20

Cargo.toml

@@ -26,7 +26,7 @@ required-features = ["rt"]
 cortex-m = "0.6.0"
 nb = "0.1.2"
 cortex-m-rt = "0.6.8"
-stm32f1 = "0.9.0"
+stm32f1 = "0.10.0"
 as-slice = "0.1"
 
 [dependencies.void]

examples/exti.rs

@@ -15,7 +15,6 @@ use stm32f1xx_hal::{
 use cortex_m_rt::entry;
 use pac::interrupt;
 use core::mem::MaybeUninit;
-use embedded_hal::digital::v2::OutputPin;
 use stm32f1xx_hal::gpio::*;
 
 // These two are owned by the ISR. main() may only access them during the initialization phase,
@@ -31,7 +30,7 @@ fn EXTI9_5() {
     let int_pin = unsafe { &mut *INT_PIN.as_mut_ptr()};
 
     if int_pin.check_interrupt() {
-        led.toggle();
+        led.toggle().unwrap();
 
         // if we don't clear this bit, the ISR would trigger indefinitely
         int_pin.clear_interrupt_pending_bit();
@@ -42,7 +41,7 @@ fn EXTI9_5() {
 fn main() -> ! {
     // initialization phase
     let p = pac::Peripherals::take().unwrap();
-    let cp = cortex_m::peripheral::Peripherals::take().unwrap();
+    let _cp = cortex_m::peripheral::Peripherals::take().unwrap();
     {
         // the scope ensures that the int_pin reference is dropped before the first ISR can be executed.
 
@@ -61,8 +60,7 @@ fn main() -> ! {
         int_pin.enable_interrupt(&p.EXTI);
     } // initialization ends here
 
-    let mut nvic = cp.NVIC;
-    nvic.enable(pac::Interrupt::EXTI9_5);
+    unsafe { pac::NVIC::unmask(pac::Interrupt::EXTI9_5); }
 
     loop {}
 }