i2c.rs 18 KB

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  1. //! Inter-Integrated Circuit (I2C) bus
  2. // This document describes a correct i2c implementation and is what
  3. // parts of this code is based on
  4. // https://www.st.com/content/ccc/resource/technical/document/application_note/5d/ae/a3/6f/08/69/4e/9b/CD00209826.pdf/files/CD00209826.pdf/jcr:content/translations/en.CD00209826.pdf
  5. use crate::afio::MAPR;
  6. use crate::gpio::gpiob::{PB10, PB11, PB6, PB7, PB8, PB9};
  7. use crate::gpio::{Alternate, OpenDrain};
  8. use crate::hal::blocking::i2c::{Read, Write, WriteRead};
  9. use crate::pac::{DWT, I2C1, I2C2};
  10. use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset};
  11. use crate::time::Hertz;
  12. use nb::Error::{Other, WouldBlock};
  13. use nb::{Error as NbError, Result as NbResult};
  14. /// I2C error
  15. #[derive(Debug, Eq, PartialEq)]
  16. pub enum Error {
  17. /// Bus error
  18. Bus,
  19. /// Arbitration loss
  20. Arbitration,
  21. /// No ack received
  22. Acknowledge,
  23. /// Overrun/underrun
  24. Overrun,
  25. // Pec, // SMBUS mode only
  26. // Timeout, // SMBUS mode only
  27. // Alert, // SMBUS mode only
  28. #[doc(hidden)]
  29. _Extensible,
  30. }
  31. #[derive(Debug, Eq, PartialEq)]
  32. pub enum DutyCycle {
  33. Ratio2to1,
  34. Ratio16to9,
  35. }
  36. #[derive(Debug, PartialEq)]
  37. pub enum Mode {
  38. Standard {
  39. frequency: Hertz,
  40. },
  41. Fast {
  42. frequency: Hertz,
  43. duty_cycle: DutyCycle,
  44. },
  45. }
  46. impl Mode {
  47. pub fn standard<F: Into<Hertz>>(frequency: F) -> Self {
  48. Mode::Standard {
  49. frequency: frequency.into(),
  50. }
  51. }
  52. pub fn fast<F: Into<Hertz>>(frequency: F, duty_cycle: DutyCycle) -> Self {
  53. Mode::Fast {
  54. frequency: frequency.into(),
  55. duty_cycle,
  56. }
  57. }
  58. pub fn get_frequency(&self) -> Hertz {
  59. match self {
  60. &Mode::Standard { frequency } => frequency,
  61. &Mode::Fast { frequency, .. } => frequency,
  62. }
  63. }
  64. }
  65. /// Helper trait to ensure that the correct I2C pins are used for the corresponding interface
  66. pub trait Pins<I2C> {
  67. const REMAP: bool;
  68. }
  69. impl Pins<I2C1> for (PB6<Alternate<OpenDrain>>, PB7<Alternate<OpenDrain>>) {
  70. const REMAP: bool = false;
  71. }
  72. impl Pins<I2C1> for (PB8<Alternate<OpenDrain>>, PB9<Alternate<OpenDrain>>) {
  73. const REMAP: bool = true;
  74. }
  75. impl Pins<I2C2> for (PB10<Alternate<OpenDrain>>, PB11<Alternate<OpenDrain>>) {
  76. const REMAP: bool = false;
  77. }
  78. /// I2C peripheral operating in master mode
  79. pub struct I2c<I2C, PINS> {
  80. i2c: I2C,
  81. pins: PINS,
  82. mode: Mode,
  83. pclk1: u32,
  84. }
  85. /// embedded-hal compatible blocking I2C implementation
  86. pub struct BlockingI2c<I2C, PINS> {
  87. nb: I2c<I2C, PINS>,
  88. start_timeout: u32,
  89. start_retries: u8,
  90. addr_timeout: u32,
  91. data_timeout: u32,
  92. }
  93. impl<PINS> I2c<I2C1, PINS> {
  94. /// Creates a generic I2C1 object on pins PB6 and PB7 or PB8 and PB9 (if remapped)
  95. pub fn i2c1(
  96. i2c: I2C1,
  97. pins: PINS,
  98. mapr: &mut MAPR,
  99. mode: Mode,
  100. clocks: Clocks,
  101. apb: &mut <I2C1 as RccBus>::Bus,
  102. ) -> Self
  103. where
  104. PINS: Pins<I2C1>,
  105. {
  106. mapr.modify_mapr(|_, w| w.i2c1_remap().bit(PINS::REMAP));
  107. I2c::_i2c1(i2c, pins, mode, clocks, apb)
  108. }
  109. }
  110. impl<PINS> BlockingI2c<I2C1, PINS> {
  111. /// Creates a blocking I2C1 object on pins PB6 and PB7 or PB8 and PB9 using the embedded-hal `BlockingI2c` trait.
  112. pub fn i2c1(
  113. i2c: I2C1,
  114. pins: PINS,
  115. mapr: &mut MAPR,
  116. mode: Mode,
  117. clocks: Clocks,
  118. apb: &mut <I2C1 as RccBus>::Bus,
  119. start_timeout_us: u32,
  120. start_retries: u8,
  121. addr_timeout_us: u32,
  122. data_timeout_us: u32,
  123. ) -> Self
  124. where
  125. PINS: Pins<I2C1>,
  126. {
  127. mapr.modify_mapr(|_, w| w.i2c1_remap().bit(PINS::REMAP));
  128. BlockingI2c::_i2c1(
  129. i2c,
  130. pins,
  131. mode,
  132. clocks,
  133. apb,
  134. start_timeout_us,
  135. start_retries,
  136. addr_timeout_us,
  137. data_timeout_us,
  138. )
  139. }
  140. }
  141. impl<PINS> I2c<I2C2, PINS> {
  142. /// Creates a generic I2C2 object on pins PB10 and PB11 using the embedded-hal `BlockingI2c` trait.
  143. pub fn i2c2(
  144. i2c: I2C2,
  145. pins: PINS,
  146. mode: Mode,
  147. clocks: Clocks,
  148. apb: &mut <I2C2 as RccBus>::Bus,
  149. ) -> Self
  150. where
  151. PINS: Pins<I2C2>,
  152. {
  153. I2c::_i2c2(i2c, pins, mode, clocks, apb)
  154. }
  155. }
  156. impl<PINS> BlockingI2c<I2C2, PINS> {
  157. /// Creates a blocking I2C2 object on pins PB10 and PB1
  158. pub fn i2c2(
  159. i2c: I2C2,
  160. pins: PINS,
  161. mode: Mode,
  162. clocks: Clocks,
  163. apb: &mut <I2C2 as RccBus>::Bus,
  164. start_timeout_us: u32,
  165. start_retries: u8,
  166. addr_timeout_us: u32,
  167. data_timeout_us: u32,
  168. ) -> Self
  169. where
  170. PINS: Pins<I2C2>,
  171. {
  172. BlockingI2c::_i2c2(
  173. i2c,
  174. pins,
  175. mode,
  176. clocks,
  177. apb,
  178. start_timeout_us,
  179. start_retries,
  180. addr_timeout_us,
  181. data_timeout_us,
  182. )
  183. }
  184. }
  185. /// Generates a blocking I2C instance from a universal I2C object
  186. fn blocking_i2c<I2C, PINS>(
  187. i2c: I2c<I2C, PINS>,
  188. clocks: Clocks,
  189. start_timeout_us: u32,
  190. start_retries: u8,
  191. addr_timeout_us: u32,
  192. data_timeout_us: u32,
  193. ) -> BlockingI2c<I2C, PINS> {
  194. let sysclk_mhz = clocks.sysclk().0 / 1_000_000;
  195. return BlockingI2c {
  196. nb: i2c,
  197. start_timeout: start_timeout_us * sysclk_mhz,
  198. start_retries,
  199. addr_timeout: addr_timeout_us * sysclk_mhz,
  200. data_timeout: data_timeout_us * sysclk_mhz,
  201. };
  202. }
  203. macro_rules! wait_for_flag {
  204. ($i2c:expr, $flag:ident) => {{
  205. let sr1 = $i2c.sr1.read();
  206. if sr1.berr().bit_is_set() {
  207. Err(Other(Error::Bus))
  208. } else if sr1.arlo().bit_is_set() {
  209. Err(Other(Error::Arbitration))
  210. } else if sr1.af().bit_is_set() {
  211. Err(Other(Error::Acknowledge))
  212. } else if sr1.ovr().bit_is_set() {
  213. Err(Other(Error::Overrun))
  214. } else if sr1.$flag().bit_is_set() {
  215. Ok(())
  216. } else {
  217. Err(WouldBlock)
  218. }
  219. }};
  220. }
  221. macro_rules! busy_wait {
  222. ($nb_expr:expr, $exit_cond:expr) => {{
  223. loop {
  224. let res = $nb_expr;
  225. if res != Err(WouldBlock) {
  226. break res;
  227. }
  228. if $exit_cond {
  229. break res;
  230. }
  231. }
  232. }};
  233. }
  234. macro_rules! busy_wait_cycles {
  235. ($nb_expr:expr, $cycles:expr) => {{
  236. let started = DWT::get_cycle_count();
  237. let cycles = $cycles;
  238. busy_wait!(
  239. $nb_expr,
  240. DWT::get_cycle_count().wrapping_sub(started) >= cycles
  241. )
  242. }};
  243. }
  244. // Generate the same code for both I2Cs
  245. macro_rules! hal {
  246. ($($I2CX:ident: ($i2cX:ident),)+) => {
  247. $(
  248. impl<PINS> I2c<$I2CX, PINS> {
  249. /// Configures the I2C peripheral to work in master mode
  250. fn $i2cX(
  251. i2c: $I2CX,
  252. pins: PINS,
  253. mode: Mode,
  254. clocks: Clocks,
  255. apb: &mut <$I2CX as RccBus>::Bus,
  256. ) -> Self {
  257. $I2CX::enable(apb);
  258. $I2CX::reset(apb);
  259. let pclk1 = <$I2CX as RccBus>::Bus::get_frequency(&clocks).0;
  260. assert!(mode.get_frequency().0 <= 400_000);
  261. let mut i2c = I2c { i2c, pins, mode, pclk1 };
  262. i2c.init();
  263. i2c
  264. }
  265. /// Initializes I2C. Configures the `I2C_TRISE`, `I2C_CRX`, and `I2C_CCR` registers
  266. /// according to the system frequency and I2C mode.
  267. fn init(&mut self) {
  268. let freq = self.mode.get_frequency();
  269. let pclk1_mhz = (self.pclk1 / 1000000) as u16;
  270. self.i2c.cr2.write(|w| unsafe {
  271. w.freq().bits(pclk1_mhz as u8)
  272. });
  273. self.i2c.cr1.write(|w| w.pe().clear_bit());
  274. match self.mode {
  275. Mode::Standard { .. } => {
  276. self.i2c.trise.write(|w| {
  277. w.trise().bits((pclk1_mhz + 1) as u8)
  278. });
  279. self.i2c.ccr.write(|w| unsafe {
  280. w.ccr().bits(((self.pclk1 / (freq.0 * 2)) as u16).max(4))
  281. });
  282. },
  283. Mode::Fast { ref duty_cycle, .. } => {
  284. self.i2c.trise.write(|w| {
  285. w.trise().bits((pclk1_mhz * 300 / 1000 + 1) as u8)
  286. });
  287. self.i2c.ccr.write(|w| {
  288. let (freq, duty) = match duty_cycle {
  289. &DutyCycle::Ratio2to1 => (((self.pclk1 / (freq.0* 3)) as u16).max(1), false),
  290. &DutyCycle::Ratio16to9 => (((self.pclk1 / (freq.0 * 25)) as u16).max(1), true)
  291. };
  292. unsafe {
  293. w.ccr().bits(freq).duty().bit(duty).f_s().set_bit()
  294. }
  295. });
  296. }
  297. };
  298. self.i2c.cr1.modify(|_, w| w.pe().set_bit());
  299. }
  300. /// Perform an I2C software reset
  301. fn reset(&mut self) {
  302. self.i2c.cr1.write(|w| w.pe().set_bit().swrst().set_bit());
  303. self.i2c.cr1.reset();
  304. self.init();
  305. }
  306. /// Generate START condition
  307. fn send_start(&mut self) {
  308. self.i2c.cr1.modify(|_, w| w.start().set_bit());
  309. }
  310. /// Check if START condition is generated. If the condition is not generated, this
  311. /// method returns `WouldBlock` so the program can act accordingly
  312. /// (busy wait, async, ...)
  313. fn wait_after_sent_start(&mut self) -> NbResult<(), Error> {
  314. wait_for_flag!(self.i2c, sb)
  315. }
  316. /// Check if STOP condition is generated. If the condition is not generated, this
  317. /// method returns `WouldBlock` so the program can act accordingly
  318. /// (busy wait, async, ...)
  319. fn wait_for_stop(&mut self) -> NbResult<(), Error> {
  320. if self.i2c.cr1.read().stop().is_no_stop() {
  321. Ok(())
  322. } else {
  323. Err(WouldBlock)
  324. }
  325. }
  326. /// Sends the (7-Bit) address on the I2C bus. The 8th bit on the bus is set
  327. /// depending on wether it is a read or write transfer.
  328. fn send_addr(&self, addr: u8, read: bool) {
  329. self.i2c.dr.write(|w| { w.dr().bits(addr << 1 | (if read {1} else {0})) });
  330. }
  331. /// Generate STOP condition
  332. fn send_stop(&self) {
  333. self.i2c.cr1.modify(|_, w| w.stop().set_bit());
  334. }
  335. /// Releases the I2C peripheral and associated pins
  336. pub fn free(self) -> ($I2CX, PINS) {
  337. (self.i2c, self.pins)
  338. }
  339. }
  340. impl<PINS> BlockingI2c<$I2CX, PINS> {
  341. fn $i2cX(
  342. i2c: $I2CX,
  343. pins: PINS,
  344. mode: Mode,
  345. clocks: Clocks,
  346. apb: &mut <$I2CX as RccBus>::Bus,
  347. start_timeout_us: u32,
  348. start_retries: u8,
  349. addr_timeout_us: u32,
  350. data_timeout_us: u32
  351. ) -> Self {
  352. blocking_i2c(I2c::$i2cX(i2c, pins, mode, clocks, apb),
  353. clocks, start_timeout_us, start_retries,
  354. addr_timeout_us, data_timeout_us)
  355. }
  356. fn send_start_and_wait(&mut self) -> NbResult<(), Error> {
  357. // According to http://www.st.com/content/ccc/resource/technical/document/errata_sheet/f5/50/c9/46/56/db/4a/f6/CD00197763.pdf/files/CD00197763.pdf/jcr:content/translations/en.CD00197763.pdf
  358. // 2.14.4 Wrong behavior of I2C peripheral in master mode after a misplaced STOP
  359. let mut retries_left = self.start_retries;
  360. let mut last_ret: NbResult<(), Error> = Err(WouldBlock);
  361. while retries_left > 0 {
  362. self.nb.send_start();
  363. last_ret = busy_wait_cycles!(self.nb.wait_after_sent_start(), self.start_timeout);
  364. if let Err(_) = last_ret {
  365. self.nb.reset();
  366. } else {
  367. break;
  368. }
  369. retries_left -= 1;
  370. }
  371. last_ret
  372. }
  373. fn write_without_stop(&mut self, addr: u8, bytes: &[u8]) -> NbResult<(), Error> {
  374. self.send_start_and_wait()?;
  375. self.nb.i2c.sr1.read();
  376. self.nb.send_addr(addr, false);
  377. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, addr), self.addr_timeout)?;
  378. self.nb.i2c.sr1.read();
  379. self.nb.i2c.sr2.read();
  380. self.nb.i2c.dr.write(|w| { w.dr().bits(bytes[0]) });
  381. for byte in &bytes[1..] {
  382. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, tx_e), self.data_timeout)?;
  383. self.nb.i2c.dr.write(|w| { w.dr().bits(*byte) });
  384. }
  385. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btf), self.data_timeout)?;
  386. Ok(())
  387. }
  388. }
  389. impl<PINS> Write for BlockingI2c<$I2CX, PINS> {
  390. type Error = NbError<Error>;
  391. fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error> {
  392. self.write_without_stop(addr, bytes)?;
  393. self.nb.send_stop();
  394. busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?;
  395. Ok(())
  396. }
  397. }
  398. impl<PINS> Read for BlockingI2c<$I2CX, PINS> {
  399. type Error = NbError<Error>;
  400. fn read(&mut self, addr: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
  401. self.send_start_and_wait()?;
  402. self.nb.i2c.sr1.read();
  403. self.nb.send_addr(addr, true);
  404. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, addr), self.addr_timeout)?;
  405. match buffer.len() {
  406. 1 => {
  407. self.nb.i2c.cr1.modify(|_, w| w.ack().clear_bit());
  408. self.nb.i2c.sr1.read();
  409. self.nb.i2c.sr2.read();
  410. self.nb.send_stop();
  411. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rx_ne), self.data_timeout)?;
  412. buffer[0] = self.nb.i2c.dr.read().dr().bits();
  413. busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?;
  414. self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit());
  415. }
  416. 2 => {
  417. self.nb.i2c.cr1.modify(|_, w| w.pos().set_bit().ack().set_bit());
  418. self.nb.i2c.sr1.read();
  419. self.nb.i2c.sr2.read();
  420. self.nb.i2c.cr1.modify(|_, w| w.ack().clear_bit());
  421. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btf), self.data_timeout)?;
  422. self.nb.send_stop();
  423. buffer[0] = self.nb.i2c.dr.read().dr().bits();
  424. buffer[1] = self.nb.i2c.dr.read().dr().bits();
  425. busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?;
  426. self.nb.i2c.cr1.modify(|_, w| w.pos().clear_bit().ack().clear_bit());
  427. self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit());
  428. }
  429. buffer_len => {
  430. self.nb.i2c.sr1.read();
  431. self.nb.i2c.sr2.read();
  432. let (first_bytes, last_two_bytes) = buffer.split_at_mut(buffer_len - 3);
  433. for byte in first_bytes {
  434. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rx_ne), self.data_timeout)?;
  435. *byte = self.nb.i2c.dr.read().dr().bits();
  436. }
  437. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btf), self.data_timeout)?;
  438. self.nb.i2c.cr1.modify(|_, w| w.ack().clear_bit());
  439. last_two_bytes[0] = self.nb.i2c.dr.read().dr().bits();
  440. self.nb.send_stop();
  441. last_two_bytes[1] = self.nb.i2c.dr.read().dr().bits();
  442. busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rx_ne), self.data_timeout)?;
  443. last_two_bytes[2] = self.nb.i2c.dr.read().dr().bits();
  444. busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?;
  445. self.nb.i2c.cr1.modify(|_, w| w.ack().set_bit());
  446. }
  447. }
  448. Ok(())
  449. }
  450. }
  451. impl<PINS> WriteRead for BlockingI2c<$I2CX, PINS> {
  452. type Error = NbError<Error>;
  453. fn write_read(
  454. &mut self,
  455. addr: u8,
  456. bytes: &[u8],
  457. buffer: &mut [u8],
  458. ) -> Result<(), Self::Error> {
  459. if !bytes.is_empty() {
  460. self.write_without_stop(addr, bytes)?;
  461. }
  462. if !buffer.is_empty() {
  463. self.read(addr, buffer)?;
  464. } else if !bytes.is_empty() {
  465. self.nb.send_stop();
  466. busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?;
  467. }
  468. Ok(())
  469. }
  470. }
  471. )+
  472. }
  473. }
  474. hal! {
  475. I2C1: (_i2c1),
  476. I2C2: (_i2c2),
  477. }