spi.rs 19 KB

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  1. /*!
  2. # Serial Peripheral Interface
  3. To construct the SPI instances, use the `Spi::spiX` functions.
  4. The pin parameter is a tuple containing `(sck, miso, mosi)` which should be configured as `(Alternate<PushPull>, Input<Floating>, Alternate<PushPull>)`.
  5. As some STM32F1xx chips have 5V tolerant SPI pins, it is also possible to configure Sck and Mosi outputs as `Alternate<PushPull>`. Then
  6. a simple Pull-Up to 5V can be used to use SPI on a 5V bus without a level shifter.
  7. You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins
  8. - `SPI1` can use `(PA5, PA6, PA7)` or `(PB3, PB4, PB5)`.
  9. - `SPI2` can use `(PB13, PB14, PB15)`
  10. - `SPI3` can use `(PB3, PB4, PB5)` or `(PC10, PC11, PC12)`
  11. ## Initialisation example
  12. ```rust
  13. // Acquire the GPIOB peripheral
  14. let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
  15. let pins = (
  16. gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh),
  17. gpiob.pb14.into_floating_input(&mut gpiob.crh),
  18. gpiob.pb15.into_alternate_push_pull(&mut gpiob.crh),
  19. );
  20. let spi_mode = Mode {
  21. polarity: Polarity::IdleLow,
  22. phase: Phase::CaptureOnFirstTransition,
  23. };
  24. let spi = Spi::spi2(dp.SPI2, pins, spi_mode, 100.khz(), clocks, &mut rcc.apb1);
  25. ```
  26. */
  27. use core::ops::Deref;
  28. use core::ptr;
  29. pub use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
  30. #[cfg(any(feature = "high", feature = "connectivity"))]
  31. use crate::pac::SPI3;
  32. use crate::pac::{SPI1, SPI2};
  33. use crate::afio::MAPR;
  34. use crate::dma::dma1::{C3, C5};
  35. #[cfg(feature = "connectivity")]
  36. use crate::dma::dma2::C2;
  37. use crate::dma::{Transfer, TransferPayload, Transmit, TxDma, R};
  38. use crate::gpio::gpioa::{PA5, PA6, PA7};
  39. use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
  40. #[cfg(feature = "connectivity")]
  41. use crate::gpio::gpioc::{PC10, PC11, PC12};
  42. use crate::gpio::{Alternate, Floating, Input, OpenDrain, PushPull};
  43. use crate::rcc::{Clocks, Enable, GetBusFreq, Reset, APB1, APB2};
  44. use crate::time::Hertz;
  45. use core::sync::atomic::{self, Ordering};
  46. use embedded_dma::StaticReadBuffer;
  47. /// SPI error
  48. #[derive(Debug)]
  49. #[non_exhaustive]
  50. pub enum Error {
  51. /// Overrun occurred
  52. Overrun,
  53. /// Mode fault occurred
  54. ModeFault,
  55. /// CRC error
  56. Crc,
  57. }
  58. use core::marker::PhantomData;
  59. mod sealed {
  60. pub trait Remap {
  61. type Periph;
  62. const REMAP: bool;
  63. }
  64. pub trait Sck<REMAP> {}
  65. pub trait Miso<REMAP> {}
  66. pub trait Mosi<REMAP> {}
  67. pub struct _Sck;
  68. pub struct _Miso;
  69. pub struct _Mosi;
  70. }
  71. use sealed::{Miso, Mosi, Remap, Sck};
  72. pub trait Pins<REMAP, P> {
  73. type _Pos;
  74. }
  75. macro_rules! pins_impl {
  76. ( $( ( $($PINX:ident),+ ), ( $($TRAIT:ident),+ ), ( $($POS:ident),* ); )+ ) => {
  77. $(
  78. #[allow(unused_parens)]
  79. impl<REMAP, $($PINX,)+> Pins<REMAP, ($(sealed::$POS),+)> for ($($PINX),+)
  80. where
  81. $($PINX: $TRAIT<REMAP>,)+
  82. {
  83. type _Pos = ($(sealed::$POS),+);
  84. }
  85. )+
  86. };
  87. }
  88. pins_impl!(
  89. (SCK, MISO, MOSI), (Sck, Miso, Mosi), (_Sck, _Miso, _Mosi);
  90. (SCK, MOSI, MISO), (Sck, Mosi, Miso), (_Sck, _Mosi, _Miso);
  91. (MOSI, SCK, MISO), (Mosi, Sck, Miso), (_Mosi, _Sck, _Miso);
  92. (MOSI, MISO, SCK), (Mosi, Miso, Sck), (_Mosi, _Miso, _Sck);
  93. (MISO, MOSI, SCK), (Miso, Mosi, Sck), (_Miso, _Mosi, _Sck);
  94. (MISO, SCK, MOSI), (Miso, Sck, Mosi), (_Miso, _Sck, _Mosi);
  95. );
  96. pub struct Spi<SPI, REMAP, PINS, FRAMESIZE> {
  97. spi: SPI,
  98. pins: PINS,
  99. _remap: PhantomData<REMAP>,
  100. _framesize: PhantomData<FRAMESIZE>,
  101. }
  102. /// The bit format to send the data in
  103. #[derive(Debug, Clone, Copy)]
  104. pub enum SpiBitFormat {
  105. /// Least significant bit first
  106. LsbFirst,
  107. /// Most significant bit first
  108. MsbFirst,
  109. }
  110. /// A filler type for when the SCK pin is unnecessary
  111. pub struct NoSck;
  112. /// A filler type for when the Miso pin is unnecessary
  113. pub struct NoMiso;
  114. /// A filler type for when the Mosi pin is unnecessary
  115. pub struct NoMosi;
  116. impl<REMAP> Sck<REMAP> for NoSck {}
  117. impl<REMAP> Miso<REMAP> for NoMiso {}
  118. impl<REMAP> Mosi<REMAP> for NoMosi {}
  119. macro_rules! remap {
  120. ($name:ident, $SPIX:ident, $state:literal, $SCK:ident, $MISO:ident, $MOSI:ident) => {
  121. pub struct $name;
  122. impl Remap for $name {
  123. type Periph = $SPIX;
  124. const REMAP: bool = $state;
  125. }
  126. impl Sck<$name> for $SCK<Alternate<PushPull>> {}
  127. impl Sck<$name> for $SCK<Alternate<OpenDrain>> {}
  128. impl Miso<$name> for $MISO<Input<Floating>> {}
  129. impl Mosi<$name> for $MOSI<Alternate<PushPull>> {}
  130. impl Mosi<$name> for $MOSI<Alternate<OpenDrain>> {}
  131. };
  132. }
  133. remap!(Spi1NoRemap, SPI1, false, PA5, PA6, PA7);
  134. remap!(Spi1Remap, SPI1, true, PB3, PB4, PB5);
  135. remap!(Spi2NoRemap, SPI2, false, PB13, PB14, PB15);
  136. #[cfg(feature = "high")]
  137. remap!(Spi3NoRemap, SPI3, false, PB3, PB4, PB5);
  138. #[cfg(feature = "connectivity")]
  139. remap!(Spi3Remap, SPI3, true, PC10, PC11, PC12);
  140. impl<REMAP, PINS> Spi<SPI1, REMAP, PINS, u8> {
  141. /**
  142. Constructs an SPI instance using SPI1 in 8bit dataframe mode.
  143. The pin parameter tuple (sck, miso, mosi) should be `(PA5, PA6, PA7)` or `(PB3, PB4, PB5)` configured as `(Alternate<PushPull>, Input<Floating>, Alternate<PushPull>)`.
  144. You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins
  145. */
  146. pub fn spi1<F, POS>(
  147. spi: SPI1,
  148. pins: PINS,
  149. mapr: &mut MAPR,
  150. mode: Mode,
  151. freq: F,
  152. clocks: Clocks,
  153. apb: &mut APB2,
  154. ) -> Self
  155. where
  156. F: Into<Hertz>,
  157. REMAP: Remap<Periph = SPI1>,
  158. PINS: Pins<REMAP, POS>,
  159. {
  160. mapr.modify_mapr(|_, w| w.spi1_remap().bit(REMAP::REMAP));
  161. Spi::<SPI1, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
  162. }
  163. }
  164. impl<REMAP, PINS> Spi<SPI2, REMAP, PINS, u8> {
  165. /**
  166. Constructs an SPI instance using SPI2 in 8bit dataframe mode.
  167. The pin parameter tuple (sck, miso, mosi) should be `(PB13, PB14, PB15)` configured as `(Alternate<PushPull>, Input<Floating>, Alternate<PushPull>)`.
  168. You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins
  169. */
  170. pub fn spi2<F, POS>(
  171. spi: SPI2,
  172. pins: PINS,
  173. mode: Mode,
  174. freq: F,
  175. clocks: Clocks,
  176. apb: &mut APB1,
  177. ) -> Self
  178. where
  179. F: Into<Hertz>,
  180. REMAP: Remap<Periph = SPI2>,
  181. PINS: Pins<REMAP, POS>,
  182. {
  183. Spi::<SPI2, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
  184. }
  185. }
  186. #[cfg(any(feature = "high", feature = "connectivity"))]
  187. impl<REMAP, PINS> Spi<SPI3, REMAP, PINS, u8> {
  188. /**
  189. Constructs an SPI instance using SPI3 in 8bit dataframe mode.
  190. The pin parameter tuple (sck, miso, mosi) should be `(PB3, PB4, PB5)` or `(PC10, PC11, PC12)` configured as `(Alternate<PushPull>, Input<Floating>, Alternate<PushPull>)`.
  191. You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins
  192. */
  193. pub fn spi3<F, POS>(
  194. spi: SPI3,
  195. pins: PINS,
  196. mapr: &mut MAPR,
  197. mode: Mode,
  198. freq: F,
  199. clocks: Clocks,
  200. apb: &mut APB1,
  201. ) -> Self
  202. where
  203. F: Into<Hertz>,
  204. REMAP: Remap<Periph = SPI3>,
  205. PINS: Pins<REMAP, POS>,
  206. {
  207. mapr.modify_mapr(|_, w| w.spi3_remap().bit(REMAP::REMAP));
  208. Spi::<SPI3, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
  209. }
  210. }
  211. pub type SpiRegisterBlock = crate::pac::spi1::RegisterBlock;
  212. pub trait SpiReadWrite<T> {
  213. fn read_data_reg(&mut self) -> T;
  214. fn write_data_reg(&mut self, data: T);
  215. fn spi_write(&mut self, words: &[T]) -> Result<(), Error>;
  216. }
  217. impl<SPI, REMAP, PINS, FrameSize> SpiReadWrite<FrameSize> for Spi<SPI, REMAP, PINS, FrameSize>
  218. where
  219. SPI: Deref<Target = SpiRegisterBlock>,
  220. FrameSize: Copy,
  221. {
  222. fn read_data_reg(&mut self) -> FrameSize {
  223. // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
  224. // reading a half-word)
  225. unsafe { ptr::read_volatile(&self.spi.dr as *const _ as *const FrameSize) }
  226. }
  227. fn write_data_reg(&mut self, data: FrameSize) {
  228. // NOTE(write_volatile) see note above
  229. unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut FrameSize, data) }
  230. }
  231. // Implement write as per the "Transmit only procedure" page 712
  232. // of RM0008 Rev 20. This is more than twice as fast as the
  233. // default Write<> implementation (which reads and drops each
  234. // received value)
  235. fn spi_write(&mut self, words: &[FrameSize]) -> Result<(), Error> {
  236. // Write each word when the tx buffer is empty
  237. for word in words {
  238. loop {
  239. let sr = self.spi.sr.read();
  240. if sr.txe().bit_is_set() {
  241. // NOTE(write_volatile) see note above
  242. // unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u8, *word) }
  243. self.write_data_reg(*word);
  244. if sr.modf().bit_is_set() {
  245. return Err(Error::ModeFault);
  246. }
  247. break;
  248. }
  249. }
  250. }
  251. // Wait for final TXE
  252. loop {
  253. let sr = self.spi.sr.read();
  254. if sr.txe().bit_is_set() {
  255. break;
  256. }
  257. }
  258. // Wait for final !BSY
  259. loop {
  260. let sr = self.spi.sr.read();
  261. if !sr.bsy().bit_is_set() {
  262. break;
  263. }
  264. }
  265. // Clear OVR set due to dropped received values
  266. // NOTE(read_volatile) see note above
  267. // unsafe {
  268. // let _ = ptr::read_volatile(&self.spi.dr as *const _ as *const u8);
  269. // }
  270. let _ = self.read_data_reg();
  271. let _ = self.spi.sr.read();
  272. Ok(())
  273. }
  274. }
  275. impl<SPI, REMAP, PINS, FrameSize> Spi<SPI, REMAP, PINS, FrameSize>
  276. where
  277. SPI: Deref<Target = SpiRegisterBlock>,
  278. FrameSize: Copy,
  279. {
  280. #[deprecated(since = "0.6.0", note = "Please use release instead")]
  281. pub fn free(self) -> (SPI, PINS) {
  282. self.release()
  283. }
  284. pub fn release(self) -> (SPI, PINS) {
  285. (self.spi, self.pins)
  286. }
  287. /// Select which frame format is used for data transfers
  288. pub fn bit_format(&mut self, format: SpiBitFormat) {
  289. match format {
  290. SpiBitFormat::LsbFirst => self.spi.cr1.modify(|_, w| w.lsbfirst().set_bit()),
  291. SpiBitFormat::MsbFirst => self.spi.cr1.modify(|_, w| w.lsbfirst().clear_bit()),
  292. }
  293. }
  294. }
  295. impl<SPI, REMAP, PINS> Spi<SPI, REMAP, PINS, u8>
  296. where
  297. SPI: Deref<Target = SpiRegisterBlock> + Enable + Reset,
  298. SPI::Bus: GetBusFreq,
  299. {
  300. fn _spi(
  301. spi: SPI,
  302. pins: PINS,
  303. mode: Mode,
  304. freq: Hertz,
  305. clocks: Clocks,
  306. apb: &mut SPI::Bus,
  307. ) -> Self {
  308. // enable or reset SPI
  309. SPI::enable(apb);
  310. SPI::reset(apb);
  311. // disable SS output
  312. spi.cr2.write(|w| w.ssoe().clear_bit());
  313. let br = match SPI::Bus::get_frequency(&clocks).0 / freq.0 {
  314. 0 => unreachable!(),
  315. 1..=2 => 0b000,
  316. 3..=5 => 0b001,
  317. 6..=11 => 0b010,
  318. 12..=23 => 0b011,
  319. 24..=47 => 0b100,
  320. 48..=95 => 0b101,
  321. 96..=191 => 0b110,
  322. _ => 0b111,
  323. };
  324. spi.cr1.write(|w| {
  325. w
  326. // clock phase from config
  327. .cpha()
  328. .bit(mode.phase == Phase::CaptureOnSecondTransition)
  329. // clock polarity from config
  330. .cpol()
  331. .bit(mode.polarity == Polarity::IdleHigh)
  332. // mstr: master configuration
  333. .mstr()
  334. .set_bit()
  335. // baudrate value
  336. .br()
  337. .bits(br)
  338. // lsbfirst: MSB first
  339. .lsbfirst()
  340. .clear_bit()
  341. // ssm: enable software slave management (NSS pin free for other uses)
  342. .ssm()
  343. .set_bit()
  344. // ssi: set nss high = master mode
  345. .ssi()
  346. .set_bit()
  347. // dff: 8 bit frames
  348. .dff()
  349. .clear_bit()
  350. // bidimode: 2-line unidirectional
  351. .bidimode()
  352. .clear_bit()
  353. // both TX and RX are used
  354. .rxonly()
  355. .clear_bit()
  356. // spe: enable the SPI bus
  357. .spe()
  358. .set_bit()
  359. });
  360. Spi {
  361. spi,
  362. pins,
  363. _remap: PhantomData,
  364. _framesize: PhantomData,
  365. }
  366. }
  367. /// Converts from 8bit dataframe to 16bit.
  368. pub fn frame_size_16bit(self) -> Spi<SPI, REMAP, PINS, u16> {
  369. self.spi.cr1.modify(|_, w| w.spe().clear_bit());
  370. self.spi.cr1.modify(|_, w| w.dff().set_bit());
  371. self.spi.cr1.modify(|_, w| w.spe().set_bit());
  372. Spi {
  373. spi: self.spi,
  374. pins: self.pins,
  375. _remap: PhantomData,
  376. _framesize: PhantomData,
  377. }
  378. }
  379. }
  380. impl<SPI, REMAP, PINS> Spi<SPI, REMAP, PINS, u16>
  381. where
  382. SPI: Deref<Target = SpiRegisterBlock>,
  383. {
  384. /// Converts from 16bit dataframe to 8bit.
  385. pub fn frame_size_8bit(self) -> Spi<SPI, REMAP, PINS, u8> {
  386. self.spi.cr1.modify(|_, w| w.spe().clear_bit());
  387. self.spi.cr1.modify(|_, w| w.dff().clear_bit());
  388. self.spi.cr1.modify(|_, w| w.spe().set_bit());
  389. Spi {
  390. spi: self.spi,
  391. pins: self.pins,
  392. _remap: PhantomData,
  393. _framesize: PhantomData,
  394. }
  395. }
  396. }
  397. impl<SPI, REMAP, PINS, FrameSize> crate::hal::spi::FullDuplex<FrameSize>
  398. for Spi<SPI, REMAP, PINS, FrameSize>
  399. where
  400. SPI: Deref<Target = SpiRegisterBlock>,
  401. FrameSize: Copy,
  402. {
  403. type Error = Error;
  404. fn read(&mut self) -> nb::Result<FrameSize, Error> {
  405. let sr = self.spi.sr.read();
  406. Err(if sr.ovr().bit_is_set() {
  407. nb::Error::Other(Error::Overrun)
  408. } else if sr.modf().bit_is_set() {
  409. nb::Error::Other(Error::ModeFault)
  410. } else if sr.crcerr().bit_is_set() {
  411. nb::Error::Other(Error::Crc)
  412. } else if sr.rxne().bit_is_set() {
  413. // NOTE(read_volatile) read only 1 byte (the svd2rust API only allows
  414. // reading a half-word)
  415. return Ok(self.read_data_reg());
  416. } else {
  417. nb::Error::WouldBlock
  418. })
  419. }
  420. fn send(&mut self, data: FrameSize) -> nb::Result<(), Error> {
  421. let sr = self.spi.sr.read();
  422. Err(if sr.ovr().bit_is_set() {
  423. nb::Error::Other(Error::Overrun)
  424. } else if sr.modf().bit_is_set() {
  425. nb::Error::Other(Error::ModeFault)
  426. } else if sr.crcerr().bit_is_set() {
  427. nb::Error::Other(Error::Crc)
  428. } else if sr.txe().bit_is_set() {
  429. // NOTE(write_volatile) see note above
  430. self.write_data_reg(data);
  431. return Ok(());
  432. } else {
  433. nb::Error::WouldBlock
  434. })
  435. }
  436. }
  437. impl<SPI, REMAP, PINS, FrameSize> crate::hal::blocking::spi::transfer::Default<FrameSize>
  438. for Spi<SPI, REMAP, PINS, FrameSize>
  439. where
  440. SPI: Deref<Target = SpiRegisterBlock>,
  441. FrameSize: Copy,
  442. {
  443. }
  444. impl<SPI, REMAP, PINS> crate::hal::blocking::spi::Write<u8> for Spi<SPI, REMAP, PINS, u8>
  445. where
  446. SPI: Deref<Target = SpiRegisterBlock>,
  447. {
  448. type Error = Error;
  449. // Implement write as per the "Transmit only procedure" page 712
  450. // of RM0008 Rev 20. This is more than twice as fast as the
  451. // default Write<> implementation (which reads and drops each
  452. // received value)
  453. fn write(&mut self, words: &[u8]) -> Result<(), Error> {
  454. self.spi_write(words)
  455. }
  456. }
  457. impl<SPI, REMAP, PINS> crate::hal::blocking::spi::Write<u16> for Spi<SPI, REMAP, PINS, u16>
  458. where
  459. SPI: Deref<Target = SpiRegisterBlock>,
  460. {
  461. type Error = Error;
  462. fn write(&mut self, words: &[u16]) -> Result<(), Error> {
  463. self.spi_write(words)
  464. }
  465. }
  466. // DMA
  467. pub struct SpiPayload<SPI, REMAP, PINS> {
  468. spi: Spi<SPI, REMAP, PINS, u8>,
  469. }
  470. pub type SpiTxDma<SPI, REMAP, PINS, CHANNEL> = TxDma<SpiPayload<SPI, REMAP, PINS>, CHANNEL>;
  471. macro_rules! spi_dma {
  472. ($SPIi:ident, $TCi:ident) => {
  473. impl<REMAP, PINS> Transmit for SpiTxDma<$SPIi, REMAP, PINS, $TCi> {
  474. type TxChannel = $TCi;
  475. type ReceivedWord = u8;
  476. }
  477. impl<REMAP, PINS> Spi<$SPIi, REMAP, PINS, u8> {
  478. pub fn with_tx_dma(self, channel: $TCi) -> SpiTxDma<$SPIi, REMAP, PINS, $TCi> {
  479. let payload = SpiPayload { spi: self };
  480. SpiTxDma { payload, channel }
  481. }
  482. }
  483. impl<REMAP, PINS> TransferPayload for SpiTxDma<$SPIi, REMAP, PINS, $TCi> {
  484. fn start(&mut self) {
  485. self.payload
  486. .spi
  487. .spi
  488. .cr2
  489. .modify(|_, w| w.txdmaen().set_bit());
  490. self.channel.start();
  491. }
  492. fn stop(&mut self) {
  493. self.payload
  494. .spi
  495. .spi
  496. .cr2
  497. .modify(|_, w| w.txdmaen().clear_bit());
  498. self.channel.stop();
  499. }
  500. }
  501. impl<B, REMAP, PIN> crate::dma::WriteDma<B, u8> for SpiTxDma<$SPIi, REMAP, PIN, $TCi>
  502. where
  503. B: StaticReadBuffer<Word = u8>,
  504. {
  505. fn write(mut self, buffer: B) -> Transfer<R, B, Self> {
  506. // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
  507. // until the end of the transfer.
  508. let (ptr, len) = unsafe { buffer.static_read_buffer() };
  509. self.channel.set_peripheral_address(
  510. unsafe { &(*$SPIi::ptr()).dr as *const _ as u32 },
  511. false,
  512. );
  513. self.channel.set_memory_address(ptr as u32, true);
  514. self.channel.set_transfer_length(len);
  515. atomic::compiler_fence(Ordering::Release);
  516. self.channel.ch().cr.modify(|_, w| {
  517. w
  518. // memory to memory mode disabled
  519. .mem2mem()
  520. .clear_bit()
  521. // medium channel priority level
  522. .pl()
  523. .medium()
  524. // 8-bit memory size
  525. .msize()
  526. .bits8()
  527. // 8-bit peripheral size
  528. .psize()
  529. .bits8()
  530. // circular mode disabled
  531. .circ()
  532. .clear_bit()
  533. // read from memory
  534. .dir()
  535. .set_bit()
  536. });
  537. self.start();
  538. Transfer::r(buffer, self)
  539. }
  540. }
  541. };
  542. }
  543. spi_dma!(SPI1, C3);
  544. spi_dma!(SPI2, C5);
  545. #[cfg(feature = "connectivity")]
  546. spi_dma!(SPI3, C2);